1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSMB_ISP__ 20 #define __MSMB_ISP__ 21 #include <linux/videodev2.h> 22 #define MAX_PLANES_PER_STREAM 3 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define MAX_NUM_STREAM 7 25 #define ISP_VERSION_47 47 26 #define ISP_VERSION_46 46 27 #define ISP_VERSION_44 44 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define ISP_VERSION_40 40 30 #define ISP_VERSION_32 32 31 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 32 #define ISP0_BIT (0x10000 << 1) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define ISP1_BIT (0x10000 << 2) 35 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 36 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 37 #define ISP_STATS_STREAM_BIT 0x80000000 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 struct msm_vfe_cfg_cmd_list; 40 enum ISP_START_PIXEL_PATTERN { 41 ISP_BAYER_RGRGRG, 42 ISP_BAYER_GRGRGR, 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 ISP_BAYER_BGBGBG, 45 ISP_BAYER_GBGBGB, 46 ISP_YUV_YCbYCr, 47 ISP_YUV_YCrYCb, 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 ISP_YUV_CbYCrY, 50 ISP_YUV_CrYCbY, 51 ISP_PIX_PATTERN_MAX 52 }; 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 enum msm_vfe_plane_fmt { 55 Y_PLANE, 56 CB_PLANE, 57 CR_PLANE, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 CRCB_PLANE, 60 CBCR_PLANE, 61 VFE_PLANE_FMT_MAX 62 }; 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 enum msm_vfe_input_src { 65 VFE_PIX_0, 66 VFE_RAW_0, 67 VFE_RAW_1, 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 VFE_RAW_2, 70 VFE_SRC_MAX, 71 }; 72 enum msm_vfe_axi_stream_src { 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 PIX_ENCODER, 75 PIX_VIEWFINDER, 76 PIX_VIDEO, 77 CAMIF_RAW, 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 IDEAL_RAW, 80 RDI_INTF_0, 81 RDI_INTF_1, 82 RDI_INTF_2, 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 VFE_AXI_SRC_MAX 85 }; 86 enum msm_vfe_frame_skip_pattern { 87 NO_SKIP, 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 EVERY_2FRAME, 90 EVERY_3FRAME, 91 EVERY_4FRAME, 92 EVERY_5FRAME, 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 EVERY_6FRAME, 95 EVERY_7FRAME, 96 EVERY_8FRAME, 97 EVERY_16FRAME, 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 EVERY_32FRAME, 100 SKIP_ALL, 101 SKIP_RANGE, 102 MAX_SKIP, 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 }; 105 enum msm_isp_stats_type { 106 MSM_ISP_STATS_AEC, 107 MSM_ISP_STATS_AF, 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 MSM_ISP_STATS_AWB, 110 MSM_ISP_STATS_RS, 111 MSM_ISP_STATS_CS, 112 MSM_ISP_STATS_IHIST, 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 MSM_ISP_STATS_SKIN, 115 MSM_ISP_STATS_BG, 116 MSM_ISP_STATS_BF, 117 MSM_ISP_STATS_BE, 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 MSM_ISP_STATS_BHIST, 120 MSM_ISP_STATS_BF_SCALE, 121 MSM_ISP_STATS_HDR_BE, 122 MSM_ISP_STATS_HDR_BHIST, 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 MSM_ISP_STATS_AEC_BG, 125 MSM_ISP_STATS_MAX 126 }; 127 struct msm_isp_sw_framskip { 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 uint32_t stats_type_mask; 130 uint32_t stream_src_mask; 131 enum msm_vfe_frame_skip_pattern skip_mode; 132 uint32_t min_frame_id; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 uint32_t max_frame_id; 135 }; 136 enum msm_vfe_testgen_color_pattern { 137 COLOR_BAR_8_COLOR, 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 UNICOLOR_WHITE, 140 UNICOLOR_YELLOW, 141 UNICOLOR_CYAN, 142 UNICOLOR_GREEN, 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 UNICOLOR_MAGENTA, 145 UNICOLOR_RED, 146 UNICOLOR_BLUE, 147 UNICOLOR_BLACK, 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 MAX_COLOR, 150 }; 151 enum msm_vfe_camif_input { 152 CAMIF_DISABLED, 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 CAMIF_PAD_REG_INPUT, 155 CAMIF_MIDDI_INPUT, 156 CAMIF_MIPI_INPUT, 157 }; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 struct msm_vfe_fetch_engine_cfg { 160 uint32_t input_format; 161 uint32_t buf_width; 162 uint32_t buf_height; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 uint32_t fetch_width; 165 uint32_t fetch_height; 166 uint32_t x_offset; 167 uint32_t y_offset; 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 uint32_t buf_stride; 170 }; 171 struct msm_vfe_camif_subsample_cfg { 172 uint32_t irq_subsample_period; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 uint32_t irq_subsample_pattern; 175 uint32_t sof_counter_step; 176 uint32_t pixel_skip; 177 uint32_t line_skip; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 }; 180 struct msm_vfe_camif_cfg { 181 uint32_t lines_per_frame; 182 uint32_t pixels_per_line; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 uint32_t first_pixel; 185 uint32_t last_pixel; 186 uint32_t first_line; 187 uint32_t last_line; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 uint32_t epoch_line0; 190 uint32_t epoch_line1; 191 uint32_t hbi_cnt; 192 enum msm_vfe_camif_input camif_input; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 struct msm_vfe_camif_subsample_cfg subsample_cfg; 195 }; 196 struct msm_vfe_testgen_cfg { 197 uint32_t lines_per_frame; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 uint32_t pixels_per_line; 200 uint32_t v_blank; 201 uint32_t h_blank; 202 enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 uint32_t rotate_period; 205 enum msm_vfe_testgen_color_pattern color_bar_pattern; 206 uint32_t burst_num_frame; 207 }; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 enum msm_vfe_inputmux { 210 CAMIF, 211 TESTGEN, 212 EXTERNAL_READ, 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 }; 215 enum msm_vfe_stats_composite_group { 216 STATS_COMPOSITE_GRP_NONE, 217 STATS_COMPOSITE_GRP_1, 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 STATS_COMPOSITE_GRP_2, 220 STATS_COMPOSITE_GRP_MAX, 221 }; 222 struct msm_vfe_pix_cfg { 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 struct msm_vfe_camif_cfg camif_cfg; 225 struct msm_vfe_testgen_cfg testgen_cfg; 226 struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; 227 enum msm_vfe_inputmux input_mux; 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 enum ISP_START_PIXEL_PATTERN pixel_pattern; 230 uint32_t input_format; 231 uint32_t is_split; 232 }; 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 struct msm_vfe_rdi_cfg { 235 uint8_t cid; 236 uint8_t frame_based; 237 }; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 struct msm_vfe_input_cfg { 240 union { 241 struct msm_vfe_pix_cfg pix_cfg; 242 struct msm_vfe_rdi_cfg rdi_cfg; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 } d; 245 enum msm_vfe_input_src input_src; 246 uint32_t input_pix_clk; 247 }; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 struct msm_vfe_fetch_eng_start { 250 uint32_t session_id; 251 uint32_t stream_id; 252 uint32_t buf_idx; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 uint32_t buf_addr; 255 }; 256 struct msm_vfe_axi_plane_cfg { 257 uint32_t output_width; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 uint32_t output_height; 260 uint32_t output_stride; 261 uint32_t output_scan_lines; 262 uint32_t output_plane_format; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 uint32_t plane_addr_offset; 265 uint8_t csid_src; 266 uint8_t rdi_cid; 267 }; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 enum msm_stream_memory_input_t { 270 MEMORY_INPUT_DISABLED, 271 MEMORY_INPUT_ENABLED 272 }; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 struct msm_vfe_axi_stream_request_cmd { 275 uint32_t session_id; 276 uint32_t stream_id; 277 uint32_t vt_enable; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 uint32_t output_format; 280 enum msm_vfe_axi_stream_src stream_src; 281 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 282 uint32_t burst_count; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 uint32_t hfr_mode; 285 uint8_t frame_base; 286 uint32_t init_frame_drop; 287 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 uint8_t buf_divert; 290 uint32_t axi_stream_handle; 291 uint32_t controllable_output; 292 uint32_t burst_len; 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 enum msm_stream_memory_input_t memory_input; 295 }; 296 struct msm_vfe_axi_stream_release_cmd { 297 uint32_t stream_handle; 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 }; 300 enum msm_vfe_axi_stream_cmd { 301 STOP_STREAM, 302 START_STREAM, 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 STOP_IMMEDIATELY, 305 }; 306 struct msm_vfe_axi_stream_cfg_cmd { 307 uint8_t num_streams; 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 uint32_t stream_handle[MAX_NUM_STREAM]; 310 enum msm_vfe_axi_stream_cmd cmd; 311 }; 312 enum msm_vfe_axi_stream_update_type { 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 ENABLE_STREAM_BUF_DIVERT, 315 DISABLE_STREAM_BUF_DIVERT, 316 UPDATE_STREAM_FRAMEDROP_PATTERN, 317 UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 UPDATE_STREAM_AXI_CONFIG, 320 UPDATE_STREAM_REQUEST_FRAMES, 321 UPDATE_STREAM_ADD_BUFQ, 322 UPDATE_STREAM_REMOVE_BUFQ, 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 UPDATE_STREAM_SW_FRAME_DROP, 325 }; 326 enum msm_vfe_iommu_type { 327 IOMMU_ATTACH, 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 IOMMU_DETACH, 330 }; 331 enum msm_vfe_buff_queue_id { 332 VFE_BUF_QUEUE_DEFAULT, 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 VFE_BUF_QUEUE_SHARED, 335 VFE_BUF_QUEUE_MAX, 336 }; 337 struct msm_vfe_axi_stream_cfg_update_info { 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 uint32_t stream_handle; 340 uint32_t output_format; 341 uint32_t user_stream_id; 342 uint32_t frame_id; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 enum msm_vfe_frame_skip_pattern skip_pattern; 345 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 346 struct msm_isp_sw_framskip sw_skip_info; 347 }; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 struct msm_vfe_axi_halt_cmd { 350 uint32_t stop_camif; 351 uint32_t overflow_detected; 352 uint32_t blocking_halt; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 }; 355 struct msm_vfe_axi_reset_cmd { 356 uint32_t blocking; 357 uint32_t frame_id; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 }; 360 struct msm_vfe_axi_restart_cmd { 361 uint32_t enable_camif; 362 }; 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 struct msm_vfe_axi_stream_update_cmd { 365 uint32_t num_streams; 366 enum msm_vfe_axi_stream_update_type update_type; 367 struct msm_vfe_axi_stream_cfg_update_info update_info[MSM_ISP_STATS_MAX]; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 }; 370 struct msm_vfe_smmu_attach_cmd { 371 uint32_t security_mode; 372 uint32_t iommu_attach_mode; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 }; 375 struct msm_vfe_stats_stream_request_cmd { 376 uint32_t session_id; 377 uint32_t stream_id; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 enum msm_isp_stats_type stats_type; 380 uint32_t composite_flag; 381 uint32_t framedrop_pattern; 382 uint32_t init_frame_drop; 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 uint32_t irq_subsample_pattern; 385 uint32_t buffer_offset; 386 uint32_t stream_handle; 387 }; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 struct msm_vfe_stats_stream_release_cmd { 390 uint32_t stream_handle; 391 }; 392 struct msm_vfe_stats_stream_cfg_cmd { 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 uint8_t num_streams; 395 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 396 uint8_t enable; 397 uint32_t stats_burst_len; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 }; 400 enum msm_vfe_reg_cfg_type { 401 VFE_WRITE, 402 VFE_WRITE_MB, 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 VFE_READ, 405 VFE_CFG_MASK, 406 VFE_WRITE_DMI_16BIT, 407 VFE_WRITE_DMI_32BIT, 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 VFE_WRITE_DMI_64BIT, 410 VFE_READ_DMI_16BIT, 411 VFE_READ_DMI_32BIT, 412 VFE_READ_DMI_64BIT, 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 GET_MAX_CLK_RATE, 415 GET_CLK_RATES, 416 GET_ISP_ID, 417 VFE_HW_UPDATE_LOCK, 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 VFE_HW_UPDATE_UNLOCK, 420 SET_WM_UB_SIZE, 421 SET_UB_POLICY, 422 }; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 struct msm_vfe_cfg_cmd2 { 425 uint16_t num_cfg; 426 uint16_t cmd_len; 427 void __user * cfg_data; 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 void __user * cfg_cmd; 430 }; 431 struct msm_vfe_cfg_cmd_list { 432 struct msm_vfe_cfg_cmd2 cfg_cmd; 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 struct msm_vfe_cfg_cmd_list * next; 435 uint32_t next_size; 436 }; 437 struct msm_vfe_reg_rw_info { 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 uint32_t reg_offset; 440 uint32_t cmd_data_offset; 441 uint32_t len; 442 }; 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 struct msm_vfe_reg_mask_info { 445 uint32_t reg_offset; 446 uint32_t mask; 447 uint32_t val; 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 }; 450 struct msm_vfe_reg_dmi_info { 451 uint32_t hi_tbl_offset; 452 uint32_t lo_tbl_offset; 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 uint32_t len; 455 }; 456 struct msm_vfe_reg_cfg_cmd { 457 union { 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 struct msm_vfe_reg_rw_info rw_info; 460 struct msm_vfe_reg_mask_info mask_info; 461 struct msm_vfe_reg_dmi_info dmi_info; 462 } u; 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 enum msm_vfe_reg_cfg_type cmd_type; 465 }; 466 enum msm_isp_buf_type { 467 ISP_PRIVATE_BUF, 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 ISP_SHARE_BUF, 470 MAX_ISP_BUF_TYPE, 471 }; 472 struct msm_isp_buf_request { 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 uint32_t session_id; 475 uint32_t stream_id; 476 uint8_t num_buf; 477 uint32_t handle; 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 enum msm_isp_buf_type buf_type; 480 }; 481 struct msm_isp_qbuf_plane { 482 uint32_t addr; 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 uint32_t offset; 485 uint32_t length; 486 }; 487 struct msm_isp_qbuf_buffer { 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; 490 uint32_t num_planes; 491 }; 492 struct msm_isp_qbuf_info { 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 uint32_t handle; 495 int32_t buf_idx; 496 struct msm_isp_qbuf_buffer buffer; 497 uint32_t dirty_buf; 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 }; 500 struct msm_isp_clk_rates { 501 uint32_t nominal_rate; 502 uint32_t high_rate; 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 }; 505 struct msm_vfe_axi_src_state { 506 enum msm_vfe_input_src input_src; 507 uint32_t src_active; 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 uint32_t src_frame_id; 510 }; 511 enum msm_isp_event_mask_index { 512 ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 ISP_EVENT_MASK_INDEX_ERROR = 1, 515 ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, 516 ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, 517 ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 ISP_EVENT_MASK_INDEX_SOF = 5, 520 ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, 521 ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, 522 ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 }; 525 #define ISP_EVENT_SUBS_MASK_NONE 0 526 #define ISP_EVENT_SUBS_MASK_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) 527 #define ISP_EVENT_SUBS_MASK_ERROR (1 << ISP_EVENT_MASK_INDEX_ERROR) 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 #define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) 530 #define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) 531 #define ISP_EVENT_SUBS_MASK_REG_UPDATE (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) 532 #define ISP_EVENT_SUBS_MASK_SOF (1 << ISP_EVENT_MASK_INDEX_SOF) 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 #define ISP_EVENT_SUBS_MASK_BUF_DIVERT (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) 535 #define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) 536 #define ISP_EVENT_SUBS_MASK_FE_READ_DONE (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) 537 enum msm_isp_event_idx { 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 ISP_REG_UPDATE = 0, 540 ISP_EPOCH_0 = 1, 541 ISP_EPOCH_1 = 2, 542 ISP_START_ACK = 3, 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 ISP_STOP_ACK = 4, 545 ISP_IRQ_VIOLATION = 5, 546 ISP_STATS_OVERFLOW = 6, 547 ISP_BUF_DONE = 7, 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 ISP_FE_RD_DONE = 8, 550 ISP_IOMMU_P_FAULT = 9, 551 ISP_ERROR = 10, 552 ISP_PING_PONG_MISMATCH = 11, 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 ISP_REG_UPDATE_MISSING = 12, 555 ISP_EVENT_MAX = 13 556 }; 557 #define ISP_EVENT_OFFSET 8 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 560 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 561 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 562 #define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 #define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) 565 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 566 #define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) 567 #define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 570 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 571 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 572 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 #define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) 575 #define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) 576 #define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) 577 #define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 580 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 581 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 582 #define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 #define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) 585 #define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) 586 #define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) 587 #define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 struct msm_isp_buf_event { 590 uint32_t session_id; 591 uint32_t stream_id; 592 uint32_t handle; 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 uint32_t output_format; 595 int8_t buf_idx; 596 }; 597 struct msm_isp_stats_event { 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 uint32_t stats_mask; 600 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; 601 }; 602 struct msm_isp_stream_ack { 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 uint32_t session_id; 605 uint32_t stream_id; 606 uint32_t handle; 607 }; 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 enum msm_vfe_error_type { 610 ISP_ERROR_NONE, 611 ISP_ERROR_CAMIF, 612 ISP_ERROR_BUS_OVERFLOW, 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 ISP_ERROR_RETURN_EMPTY_BUFFER, 615 ISP_ERROR_FRAME_ID_MISMATCH, 616 ISP_ERROR_MAX, 617 }; 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 struct msm_isp_error_info { 620 enum msm_vfe_error_type err_type; 621 uint32_t session_id; 622 uint32_t stream_id; 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 }; 625 struct msm_isp_output_info { 626 uint32_t regs_not_updated; 627 uint32_t output_err_mask; 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 uint16_t stream_framedrop_mask; 630 uint32_t stats_framedrop_mask; 631 uint32_t axi_updating_mask; 632 }; 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 struct msm_isp_event_data { 635 struct timeval timestamp; 636 struct timeval mono_timestamp; 637 uint32_t frame_id; 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 union { 640 struct msm_isp_stats_event stats; 641 struct msm_isp_buf_event buf_done; 642 struct msm_isp_error_info error_info; 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 struct msm_isp_output_info output_info; 645 } u; 646 }; 647 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 650 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 651 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 652 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 655 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 656 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 657 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 660 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 661 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 662 #define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 #define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') 665 #define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') 666 #define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') 667 #define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 #define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') 670 #define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') 671 #define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') 672 #define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 #define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') 675 #define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') 676 #define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') 677 #define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 #define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') 680 #define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') 681 #define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) 682 #define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_isp_buf_request) 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 #define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_isp_qbuf_info) 685 #define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_isp_buf_request) 686 #define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_vfe_axi_stream_request_cmd) 687 #define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_vfe_axi_stream_cfg_cmd) 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 #define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_vfe_axi_stream_release_cmd) 690 #define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vfe_input_cfg) 691 #define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_vfe_axi_src_state) 692 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_vfe_stats_stream_request_cmd) 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_vfe_stats_stream_cfg_cmd) 695 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_vfe_stats_stream_release_cmd) 696 #define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', BASE_VIDIOC_PRIVATE + 12, enum msm_vfe_input_src) 697 #define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_vfe_axi_stream_update_cmd) 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 #define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_vfe_cfg_cmd_list) 700 #define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_vfe_smmu_attach_cmd) 701 #define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_vfe_axi_stream_update_cmd) 702 #define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_vfe_axi_halt_cmd) 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 #define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_vfe_axi_reset_cmd) 705 #define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_vfe_axi_restart_cmd) 706 #define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_vfe_fetch_eng_start) 707 #define VIDIOC_MSM_ISP_DEQUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct msm_isp_qbuf_info) 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 #endif 710 711
