| /external/mesa3d/src/gallium/drivers/ilo/shader/ |
| toy_compiler.c | 245 if (dst.writemask != TOY_WRITEMASK_XYZW) {
247 if (dst.writemask & TOY_WRITEMASK_X)
249 if (dst.writemask & TOY_WRITEMASK_Y)
251 if (dst.writemask & TOY_WRITEMASK_Z)
253 if (dst.writemask & TOY_WRITEMASK_W)
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| toy_helpers.h | 66 if (dst.writemask & (1 << i)) {
68 trans[i].writemask = TOY_WRITEMASK_XYZW;
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| toy_compiler_asm.c | 50 unsigned writemask; member in struct:codegen::codegen_dst
637 /* the lower 4 bits are reserved for the writemask */
642 dst->writemask;
652 assert(dst->writemask == TOY_WRITEMASK_XYZW);
680 dst->writemask;
683 assert(dst->writemask == TOY_WRITEMASK_XYZW);
842 dst->writemask << 17 |
855 dst->writemask << 17 |
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_ir_vec4.h | 160 unsigned writemask);
162 unsigned writemask);
202 writemask(dst_reg reg, unsigned mask) function in namespace:brw
205 assert((reg.writemask & mask) != 0);
206 reg.writemask &= mask;
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| brw_fs_vector_splitting.cpp | 262 unsigned int writemask; local
269 writemask = 1;
272 writemask = 1 << i;
285 NULL, writemask));
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| brw_vec4_copy_propagation.cpp | 78 inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
144 * based on the destination writemask.
409 const unsigned dst_saturate_mask = inst->dst.writemask &
414 if (dst_saturate_mask != inst->dst.writemask)
525 entries[reg].saturatemask &= ~inst->dst.writemask;
527 if (inst->dst.writemask & (1 << i)) {
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| test_vec4_cmod_propagation.cpp | 151 dest_null.writemask = WRITEMASK_X;
415 dest_null.writemask = WRITEMASK_X;
458 dest_null.writemask = WRITEMASK_X;
490 dest_null.writemask = WRITEMASK_X;
629 dest.writemask = WRITEMASK_X;
666 dest.writemask = WRITEMASK_X;
676 dest_null.writemask = WRITEMASK_X;
708 dest.writemask = WRITEMASK_XW;
751 dest.writemask = WRITEMASK_X;
759 dest_null.writemask = WRITEMASK_X
[all...] |
| brw_reg.h | 143 * read from a swizzled source given the instruction writemask.
262 unsigned writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon28604::__anon28605
351 * \param writemask WRITEMASK_X/Y/Z/W bitfield
364 unsigned writemask)
386 * set swizzle and writemask to W, as the lower bits of subnr will
392 reg.writemask = writemask;
769 /* If/else instructions break in align16 mode if writemask & swizzle
973 reg.writemask &= mask;
981 reg.writemask = mask
[all...] |
| brw_vec4_live_variables.cpp | 103 if (inst->dst.writemask & (1 << c)) {
113 if ((inst->dst.writemask & (1 << c)) &&
271 if (inst->dst.writemask & (1 << c)) {
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| brw_vec4_nir.cpp | 376 unsigned writemask = 1 << i; local
378 if ((remaining & writemask) == 0)
386 writemask |= 1 << j;
390 reg.writemask = writemask;
397 remaining &= ~writemask;
400 /* Set final writemask */
401 reg.writemask = brw_writemask_for_size(instr->def.num_components);
421 dest.writemask = brw_writemask_for_size(instr->num_components);
496 int writemask = WRITEMASK_X local
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_glsl_to_tgsi.cpp | 198 st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, int index)
204 this->writemask = writemask;
212 st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type)
218 this->writemask = writemask;
232 this->writemask = 0;
244 unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */
276 this->writemask = WRITEMASK_XYZW;
746 * so we have to fixup destination writemask/index and src swizzle/indexes
774 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED ? inst->dst[0].writemask : inst->dst[1].writemask; local
[all...] |
| /external/mesa3d/src/mesa/program/ |
| ir_to_mesa.cpp | 103 dst_reg(gl_register_file file, int writemask)
107 this->writemask = writemask;
115 this->writemask = 0;
123 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:__anon28749::dst_reg
143 this->writemask = WRITEMASK_XYZW;
403 assert(dst.writemask != 0);
439 int done_mask = ~dst.writemask;
473 inst->dst.writemask = this_mask;
923 result_dst.writemask = (1 << ir->type->vector_elements) - 1
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_simple_shaders.h | 75 unsigned writemask,
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.c | 530 unsigned int writemask,
543 if (!writemask)
548 srcmasks[src] |= writemask;
551 srcmasks[src] |= writemask;
|
| radeon_compiler.h | 105 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask);
|
| /external/mesa3d/src/gallium/drivers/softpipe/ |
| sp_buffer.c | 144 if (params->writemask & (1 << c)) {
163 unsigned writemask,
269 if (writemask & (1 << c)) {
328 opcode, params->writemask, rgba, rgba2);
|
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_pipe_depthstencil.c | 151 /* SVGA3D has one ref/mask/writemask triple shared between front &
155 ds->stencil_writemask = templ->stencil[0].writemask & 0xff;
174 ds->stencil_writemask = templ->stencil[1].writemask & 0xff;
188 ds->zwriteenable = templ->depth.writemask;
|
| svga_tgsi_insn.c | 118 dest.mask = reg->Register.WriteMask;
1188 writemask(temp, channel),
[all...] |
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_bld_depth.c | 269 if (stencil[0].writemask != 0xff ||
270 (stencil[1].enabled && front_facing != NULL && stencil[1].writemask != 0xff)) {
271 /* mask &= stencil[0].writemask */
272 LLVMValueRef writemask = lp_build_const_int_vec(bld->gallivm, bld->type, local
273 stencil[0].writemask);
274 if (stencil[1].enabled && stencil[1].writemask != stencil[0].writemask && front_facing != NULL) {
276 stencil[1].writemask);
277 writemask = lp_build_select(bld, front_facing, writemask, back_writemask)
[all...] |
| lp_state_blend.c | 119 state->depth.writemask = 0;
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_state.c | 139 * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
140 * values, so you don't have to do a separate writemask setup.
200 if (cso->depth.writemask) {
228 tlb_stencil_setup_writemask(front->writemask);
229 uint8_t back_writemask = front->writemask;
235 back_writemask = back->writemask;
237 tlb_stencil_setup_writemask(back->writemask);
249 so->stencil_uniforms[2] = (front->writemask |
|
| /external/mesa3d/src/compiler/glsl/ |
| ir_builder.h | 29 enum writemask { enum in namespace:ir_builder
124 ir_assignment *assign(deref lhs, operand rhs, int writemask);
126 ir_assignment *assign(deref lhs, operand rhs, operand condition, int writemask);
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_scan.h | 173 ubyte writemask; member in struct:tgsi_array_info
|
| /external/mesa3d/src/gallium/state_trackers/nine/ |
| nine_pipe.c | 39 dsa.depth.writemask = !!rs[D3DRS_ZWRITEENABLE];
50 dsa.stencil[0].writemask = rs[D3DRS_STENCILWRITEMASK];
59 dsa.stencil[1].writemask = dsa.stencil[0].writemask;
|
| /external/mesa3d/src/gallium/include/pipe/ |
| p_state.h | 268 unsigned writemask:1; /**< allow depth buffer writes? */ member in struct:pipe_depth_state
284 unsigned writemask:8; member in struct:pipe_stencil_state
|
