| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_cse.cpp | 130 a->dst.writemask == b->dst.writemask &&
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| brw_vec4_tes.cpp | 246 dst.writemask = brw_writemask_for_size(instr->num_components);
274 dst.writemask = brw_writemask_for_size(instr->num_components);
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| brw_shader.h | 79 using brw_reg::writemask;
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| test_vec4_copy_propagation.cpp | 165 v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f)));
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| brw_vec4_builder.h | 353 writemask(vgrf(BRW_REGISTER_TYPE_UD), WRITEMASK_X);
606 inst->dst.writemask != WRITEMASK_XYZW) {
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_text.c | 443 uint *writemask )
451 *writemask = TGSI_WRITEMASK_NONE;
455 *writemask |= TGSI_WRITEMASK_X;
459 *writemask |= TGSI_WRITEMASK_Y;
463 *writemask |= TGSI_WRITEMASK_Z;
467 *writemask |= TGSI_WRITEMASK_W;
470 if (*writemask == TGSI_WRITEMASK_NONE) {
471 report_error( ctx, "Writemask expected" );
478 *writemask = TGSI_WRITEMASK_XYZW;
812 uint writemask; local
1314 uint writemask; local
[all...] |
| tgsi_dump.c | 221 uint writemask )
223 if (writemask != TGSI_WRITEMASK_XYZW) {
225 if (writemask & TGSI_WRITEMASK_X)
227 if (writemask & TGSI_WRITEMASK_Y)
229 if (writemask & TGSI_WRITEMASK_Z)
231 if (writemask & TGSI_WRITEMASK_W)
615 _dump_writemask( ctx, dst->Register.WriteMask );
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| tgsi_transform.h | 226 unsigned file, unsigned index, unsigned writemask)
230 reg->Register.WriteMask = writemask;
266 inst.Dst[0].Register.WriteMask = dst_writemask;
294 inst.Dst[0].Register.WriteMask = dst_writemask;
326 inst.Dst[0].Register.WriteMask = dst_writemask;
357 inst.Dst[0].Register.WriteMask = dst_writemask;
403 inst.Dst[0].Register.WriteMask = dst_writemask;
459 inst.Dst[0].Register.WriteMask = dst_writemask;
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| tgsi_exec.h | 52 ((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
144 unsigned writemask; member in struct:tgsi_buffer_params
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| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_pipe_blend.c | 118 perRT[i].renderTargetWriteMask = bs->rt[i].writemask;
324 blend->rt[i].writemask = templ->rt[i].colormask;
327 blend->rt[i].writemask = templ->rt[0].colormask;
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| svga_tgsi_emit.h | 267 * Apply a writemask to the given SVGA3dShaderDestToken, returning a
271 writemask(SVGA3dShaderDestToken dest, unsigned mask)
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| /external/mesa3d/src/compiler/glsl/ |
| ir_builder.cpp | 49 assign(deref lhs, operand rhs, operand condition, int writemask)
56 writemask);
68 assign(deref lhs, operand rhs, int writemask)
70 return assign(lhs, rhs, (ir_rvalue *) NULL, writemask);
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| /external/mesa3d/src/compiler/nir/ |
| nir_builder.h | 439 unsigned writemask)
446 nir_intrinsic_set_write_mask(store, writemask);
454 nir_ssa_def *value, unsigned writemask)
462 store->const_index[0] = writemask & ((1 << num_components) - 1);
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_simple_shaders.c | 210 * IMM {0,0,0,1} // (if writemask != 0xf)
211 * MOV TEMP[0], IMM[0] // (if writemask != 0xf)
212 * TEX TEMP[0].writemask, IN[0], SAMP[0], 2D;
219 * \param writemask mask of TGSI_WRITEMASK_x
225 unsigned writemask,
257 if (writemask != TGSI_WRITEMASK_XYZW) {
265 ureg_writemask(temp, writemask),
269 ureg_writemask(temp, writemask),
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader_tgsi_setup.c | 480 if (!(array->writemask & (1 << swizzle)))
502 lp_build_const_int32(gallivm, util_bitcount(array->writemask)),
508 util_bitcount(array->writemask & ((1 << swizzle) - 1))),
807 unsigned writemask = decl->Declaration.UsageMask; local
816 writemask &= ctx->temp_arrays[id].writemask;
817 ctx->temp_arrays[id].writemask = writemask;
818 array_size = ((last - first) + 1) * util_bitcount(writemask);
871 if (writemask != TGSI_WRITEMASK_XYZW &
[all...] |
| si_state.h | 84 uint8_t writemask[2]; member in struct:si_dsa_stencil_ref_part
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| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_state.c | 469 int writemask = depth_stencil->stencil[0].writemask & 0xff; local
475 STENCIL_WRITE_MASK(writemask));
498 int wmask = depth_stencil->stencil[1].writemask & 0xff;
534 if (depth_stencil->depth.writemask)
[all...] |
| i915_fpc_translate.c | 323 * Compute flags for saturation and writemask.
328 const uint writeMask
329 = inst->Dst[0].Register.WriteMask;
335 if (writeMask & TGSI_WRITEMASK_X)
337 if (writeMask & TGSI_WRITEMASK_Y)
339 if (writeMask & TGSI_WRITEMASK_Z)
341 if (writeMask & TGSI_WRITEMASK_W)
498 uint writemask; local
664 A0_DEST_CHANNEL_ALL, /* dest writemask */
677 A0_DEST_CHANNEL_ALL, /* dest writemask */
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| nv30_state.c | 224 SB_DATA (so, cso->depth.writemask);
237 SB_DATA (so, cso->stencil[0].writemask);
253 SB_DATA (so, cso->stencil[1].writemask);
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| /external/mesa3d/src/gallium/drivers/ilo/shader/ |
| toy_compiler_disasm.c | 55 unsigned writemask:4; member in struct:disasm_dst_operand
378 inst->dst.writemask = 0xf;
380 inst->dst.writemask = GEN_EXTRACT(dw1, GEN6_INST_DST_WRITEMASK);
565 inst->dst.writemask = GEN_EXTRACT(dw1, GEN6_3SRC_DST_WRITEMASK);
621 inst->dst.writemask = GEN_EXTRACT(dw1, GEN6_3SRC_DST_WRITEMASK);
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_cb_clear.c | 249 depth_stencil.depth.writemask = 1;
262 depth_stencil.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
373 return (ctx->Stencil.WriteMask[0] & stencilMax) == 0;
386 return (ctx->Stencil.WriteMask[0] & stencilMax) != stencilMax;
462 * This can only happen when the stencil writemask is not a full mask.
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_aos.c | 309 * Writemask
312 if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
313 LLVMValueRef writemask; local
315 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
317 reg->Register.WriteMask,
322 mask = LLVMBuildAnd(builder, mask, writemask, "");
324 mask = writemask;
491 * assume a full writemask and then let LLVM optimization passes eliminate
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| /external/mesa3d/src/gallium/drivers/softpipe/ |
| sp_quad_depth_test.c | 433 * \param wrtMask writemask controlling which bits are changed in the
517 /* apply bit-wise stencil buffer writemask */
599 /* Update our internal copy only if writemask set. Even if
600 * depth.writemask is FALSE, may still need to write out buffer
603 if (softpipe->depth_stencil->depth.writemask) {
645 wrtMask = softpipe->depth_stencil->stencil[face].writemask;
834 if (qs->softpipe->depth_stencil->depth.writemask)
915 boolean depthwrite = qs->softpipe->depth_stencil->depth.writemask;
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 170 * writemask is honoured.
172 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask)
184 inst->U.I.DstReg.WriteMask &= writemask;
255 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
266 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
281 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
335 inst_add->U.I.DstReg.WriteMask = RC_MASK_X;
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| /external/mesa3d/src/gallium/auxiliary/postprocess/ |
| pp_mlaa.c | 118 mstencil.stencil[0].valuemask = mstencil.stencil[0].writemask = ~0;
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