| /external/mesa3d/src/gallium/tests/graw/ |
| graw_util.h | 166 depthStencilAlpha.depth.writemask = 1;
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_scan.c | 805 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
809 arrays[j].writemask |= dst->Register.WriteMask;
818 array->writemask |= dst->Register.WriteMask;
880 dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
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| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_tgsi_vgpu10.c | 443 * writes we need to mask the declaration usage or instruction writemask
451 * declaration or instruction writemask.
453 * \param writemask the declaration usage mask or instruction writemask
460 unsigned writemask, unsigned clip_reg_index)
468 writemask &= ((emit->key.clip_plane_enable >> shift) & 0xf);
470 return writemask;
856 unsigned writemask = reg->Register.WriteMask; local
932 /* the operand has a writemask */
2536 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL; local
3273 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp; local
3315 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp; local
[all...] |
| svga_context.h | 112 uint8_t writemask; member in struct:svga_blend_state::__anon28239
144 /* SVGA3D has one ref/mask/writemask triple shared between front &
|
| svga_tgsi_decl_sm30.c | 193 reg = writemask( dst(emit->ps_true_pos),
|
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_state.c | 699 if (state->depth.writemask) {
726 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
744 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
751 state->stencil[0].writemask != state->stencil[1].writemask);
[all...] |
| r300_context.c | 476 dsa.depth.writemask = 1;
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_state_common.c | 269 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
273 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
292 ref.writemask[0] = dsa->writemask[0];
293 ref.writemask[1] = dsa->writemask[1];
315 ref.writemask[0] = dsa->writemask[0];
316 ref.writemask[1] = dsa->writemask[1]
[all...] |
| r600_pipe.h | 209 ubyte writemask[2]; member in struct:r600_stencil_ref
304 ubyte writemask[2]; member in struct:r600_dsa_state
|
| r600_state.c | 415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
[all...] |
| /external/mesa3d/src/gallium/drivers/ilo/shader/ |
| toy_tgsi.c | 464 if (!(dst[0].writemask & TOY_WRITEMASK_YZ))
495 if (dst[0].writemask & TOY_WRITEMASK_X) {
520 if (dst[0].writemask & TOY_WRITEMASK_XY) {
[all...] |
| toy_legalize.c | 110 /* no writemask in align1 */
111 if (inst->dst.writemask != TOY_WRITEMASK_XYZW) {
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_state.c | 368 SB_DATA (so, cso->depth.writemask);
396 SB_DATA (so, cso->stencil[0].writemask);
412 SB_DATA (so, cso->stencil[1].writemask);
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_disasm.c | 281 static const char *const writemask[16] = { variable
778 err |= control(file, "writemask", writemask,
808 err |= control(file, "writemask", writemask,
[all...] |
| brw_vec4_reg_allocate.cpp | 327 ~prev_inst->dst.writemask) == 0;
|
| brw_vec4_generator.cpp | 60 /* Can't do writemask because math can't be align16. */
61 assert(dst.writemask == WRITEMASK_XYZW);
[all...] |
| brw_fs_nir.cpp | [all...] |
| /external/mesa3d/src/mesa/main/ |
| ffvertex_prog.c | 544 dst->WriteMask = mask ? mask : WRITEMASK_XYZW;
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_dump_state.c | 514 util_dump_member(stream, bool, &state->depth, writemask);
535 util_dump_member(stream, uint, &state->stencil[i], writemask);
|
| /external/mesa3d/src/gallium/drivers/trace/ |
| tr_dump_state.c | 357 trace_dump_member(bool, &state->depth, writemask);
373 trace_dump_member(uint, &state->stencil[i], writemask);
|
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_state_fs.c | 357 if (key->stencil[0].enabled && (key->stencil[0].writemask ||
359 key->stencil[1].writemask)))
371 if (!(key->depth.enabled && key->depth.writemask) &&
372 !(key->stencil[0].enabled && (key->stencil[0].writemask ||
374 key->stencil[1].writemask))))
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_state.c | 945 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
949 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_state.c | 349 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
370 SB_DATA (so, cso->stencil[0].writemask);
384 SB_DATA (so, cso->stencil[1].writemask);
[all...] |
| /external/mesa3d/src/gallium/drivers/swr/ |
| swr_state.cpp | [all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 600 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
601 Reg writemask; member in struct:llvm::X86Disassembler::InternalInstruction
|
