| /external/swiftshader/third_party/LLVM/test/CodeGen/Alpha/ |
| ctlz.ll | 1 ; Make sure this testcase codegens to the ctlz instruction
2 ; RUN: llc < %s -march=alpha -mcpu=ev67 | grep -i ctlz
3 ; RUN: llc < %s -march=alpha -mattr=+CIX | grep -i ctlz
4 ; RUN: llc < %s -march=alpha -mcpu=ev6 | not grep -i ctlz
5 ; RUN: llc < %s -march=alpha -mattr=-CIX | not grep -i ctlz
7 declare i8 @llvm.ctlz.i8(i8)
11 %tmp.1 = call i8 @llvm.ctlz.i8( i8 %x )
|
| ctlz_e.ll | 4 declare i64 @llvm.ctlz.i64(i64)
8 %tmp.1 = call i64 @llvm.ctlz.i64( i64 %x ) ; <i64> [#uses=1]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/ |
| ctlz16.ll | 3 declare i16 @llvm.ctlz.i16(i16)
6 %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1]
10 %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1]
15 %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1]
|
| /external/clang/test/CodeGen/ |
| 2006-01-16-BitCountIntrinsicsUnsigned.c | 5 // CHECK: llvm.ctlz.i32
10 // CHECK: llvm.ctlz.i32
|
| lzcnt-builtins.c | 10 // CHECK: @llvm.ctlz.i16
16 // CHECK: @llvm.ctlz.i32
22 // CHECK: @llvm.ctlz.i64
28 // CHECK: @llvm.ctlz.i32
34 // CHECK: @llvm.ctlz.i64
|
| count-builtins.c | 10 // CHECK: call i16 @llvm.ctlz.i16
20 // CHECK: call i32 @llvm.ctlz.i32
30 // CHECK: call i64 @llvm.ctlz.i64
|
| /external/llvm/test/CodeGen/Mips/ |
| 2008-08-08-ctlz.ll | 6 call i32 @llvm.ctlz.i32( i32 %u, i1 true )
10 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
|
| 2010-11-09-CountLeading.ll | 6 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
10 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
15 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
23 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
31 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| clz.ll | 3 declare i32 @llvm.ctlz.i32(i32)
8 %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x )
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| thumb2-clz.ll | 6 %tmp = tail call i32 @llvm.ctlz.i32(i32 %a)
10 declare i32 @llvm.ctlz.i32(i32) nounwind readnone
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| lzcnt.ll | 4 %tmp = tail call i32 @llvm.ctlz.i32( i32 %x )
10 declare i32 @llvm.ctlz.i32(i32) nounwind readnone
13 %tmp = tail call i16 @llvm.ctlz.i16( i16 %x )
19 declare i16 @llvm.ctlz.i16(i16) nounwind readnone
22 %tmp = tail call i64 @llvm.ctlz.i64( i64 %x )
28 declare i64 @llvm.ctlz.i64(i64) nounwind readnone
31 %tmp = tail call i8 @llvm.ctlz.i8( i8 %x )
37 declare i8 @llvm.ctlz.i8(i8) nounwind readnone
|
| clz.ll | 4 %tmp = tail call i32 @llvm.ctlz.i32( i32 %x )
11 declare i32 @llvm.ctlz.i32(i32) nounwind readnone
26 %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1 ) ; <i16> [#uses=1]
33 declare i16 @llvm.ctlz.i16(i16) nounwind readnone
46 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or)
|
| /external/llvm/test/CodeGen/NVPTX/ |
| ctlz.ll | 5 declare i16 @llvm.ctlz.i16(i16, i1) readnone
6 declare i32 @llvm.ctlz.i32(i32, i1) readnone
7 declare i64 @llvm.ctlz.i64(i64, i1) readnone
11 %val = call i32 @llvm.ctlz.i32(i32 %a, i1 false) readnone
17 %val = call i16 @llvm.ctlz.i16(i16 %a, i1 false) readnone
23 %val = call i64 @llvm.ctlz.i64(i64 %a, i1 false) readnone
30 %val = call i32 @llvm.ctlz.i32(i32 %a, i1 true) readnone
36 %val = call i16 @llvm.ctlz.i16(i16 %a, i1 true) readnone
42 %val = call i64 @llvm.ctlz.i64(i64 %a, i1 true) readnone
|
| /external/llvm/test/CodeGen/X86/ |
| lzcnt.ll | 3 declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
4 declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone
5 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
6 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
9 %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
16 %tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
23 %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
30 %tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
37 %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
44 %tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true
[all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| ctlz.ll | 5 declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone
6 declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
7 declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone
9 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
10 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
11 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
13 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
14 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
15 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone
21 ; SI-DAG: s_flbit_i32_b32 [[CTLZ:s[0-9]+]], [[VAL]
[all...] |
| ctlz_zero_undef.ll | 5 declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
7 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
8 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
9 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
11 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
12 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
13 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone
26 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
27 store i32 %ctlz, i32 addrspace(1)* %out, align
[all...] |
| /external/llvm/test/Analysis/CostModel/X86/ |
| ctbits-cost.ll | 94 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
95 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)
96 declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)
97 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)
99 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1)
100 declare <8 x i32> @llvm.ctlz.v8i32(<8 x i32>, i1)
101 declare <16 x i16> @llvm.ctlz.v16i16(<16 x i16>, i1)
102 declare <32 x i8> @llvm.ctlz.v32i8(<32 x i8>, i1)
106 ; SSE: Found an estimated cost of 6 for instruction: %ctlz
107 ; AVX: Found an estimated cost of 6 for instruction: %ctlz
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| clz.ll | 3 declare i32 @llvm.ctlz.i32(i32, i1)
8 %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
|
| /external/llvm/test/CodeGen/PowerPC/ |
| vec_clz.ll | 5 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone
6 declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone
7 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readnone
8 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone
11 %vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x)
19 %vcnt = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x)
27 %vcnt = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x)
35 %vcnt = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x)
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-clz.ll | 6 %tmp = tail call i32 @llvm.ctlz.i32(i32 %a, i1 true)
10 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| 2010-11-09-CountLeading.ll | 6 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X)
10 declare i32 @llvm.ctlz.i32(i32) nounwind readnone
15 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X)
23 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg)
31 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg)
|
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-ctlz-01.ll | 5 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 %is_zero_undef)
6 declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 %is_zero_undef)
7 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 %is_zero_undef)
8 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 %is_zero_undef)
15 %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false)
24 %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 true)
33 %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false)
42 %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 true)
51 %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false)
60 %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 true
[all...] |
| /external/llvm/test/Verifier/ |
| cttz-undef-arg.ll | 3 declare i32 @llvm.ctlz.i32(i32, i1)
9 ; CHECK-NEXT: @llvm.ctlz.i32
10 call i32 @llvm.ctlz.i32(i32 %x, i1 %is_not_zero)
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vclz.ll | 7 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
15 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
23 %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
31 %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
39 %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
47 %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
53 %vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
59 %vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
67 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
75 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwin
[all...] |
| /external/clang/test/CodeGenOpenCL/ |
| builtins-generic-amdgcn.cl | 5 // CHECK: tail call i32 @llvm.ctlz.i32(i32 %a, i1 true)
12 // CHECK: tail call i64 @llvm.ctlz.i64(i64 %a, i1 true)
|
