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  /external/valgrind/none/tests/mips64/
rotate_swap.c 78 printf("--- DROTR32 ---\n");
79 TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 16);
80 TESTINST_DROTR("drotr32", 0xffff0000ffffffff, 16);
81 TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 8);
82 TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 4);
83 TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 5);
84 TESTINST_DROTR("drotr32", 0x31415927ffffffff, 10);
85 TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 4);
86 TESTINST_DROTR("drotr32", 0x2000ffffffffffff, 0);
87 TESTINST_DROTR("drotr32", 0xeeeeffffffffffff, 16)
    [all...]
shift_instructions.stdout.exp-mips64r2     [all...]
rotate_swap.stdout.exp-mips64r2 22 --- DROTR32 ---
23 drotr32 :: in 0x2000ffffffffffff, out 0xffffffffffff2000, SA 16
24 drotr32 :: in 0xffff0000ffffffff, out 0xffffffffffff, SA 16
25 drotr32 :: in 0x2000ffffffffffff, out 0xffffffffff2000ff, SA 8
26 drotr32 :: in 0x2000ffffffffffff, out 0xfffffffff2000fff, SA 4
27 drotr32 :: in 0x2000ffffffffffff, out 0xfffffffff90007ff, SA 5
28 drotr32 :: in 0x31415927ffffffff, out 0x49ffffffffcc5056, SA 10
29 drotr32 :: in 0x2000ffffffffffff, out 0xfffffffff2000fff, SA 4
30 drotr32 :: in 0x2000ffffffffffff, out 0xffffffff2000ffff, SA 0
31 drotr32 :: in 0xeeeeffffffffffff, out 0xffffffffffffeeee, SA 1
    [all...]
shift_instructions.c 6 DROTR=0, DROTR32, DROTRV, DSLL,
34 case DROTR32:
37 TEST2("drotr32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
38 TEST2("drotr32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
39 TEST2("drotr32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
40 TEST2("drotr32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
41 TEST2("drotr32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
42 TEST2("drotr32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
43 TEST2("drotr32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
44 TEST2("drotr32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1)
    [all...]
  /external/llvm/test/MC/Mips/
set-mips-directives.s 31 drotr32 $1,$14,15
34 drotr32 $1,$14,15
37 drotr32 $1,$14,15
67 # CHECK: drotr32 $1, $14, 15
70 # CHECK: drotr32 $1, $14, 15
73 # CHECK: drotr32 $1, $14, 15
set-arch.s 30 drotr32 $1, $14, 15
33 drotr32 $1, $14, 15
36 drotr32 $1, $14, 15
63 # CHECK: drotr32 $1, $14, 15
rotations64.s 108 # CHECK-64R: drotr32 $4, $4, 31 # encoding: [0x00,0x24,0x27,0xfe]
116 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe]
121 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e]
126 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e]
144 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe]
149 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e]
154 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e]
200 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e]
205 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e]
210 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe
    [all...]
set-mips-directives-bad.s 33 drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled
mips64-alu-instructions.s 77 # CHECK: drotr32 $9, $6, 20 # encoding: [0x3e,0x4d,0x26,0x00]
102 drotr32 $9, $6, 20
  /external/llvm/test/MC/Mips/mips64r3/
invalid.s 11 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
12 drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
valid.s 98 drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe]
99 drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
mips64r2.s 55 drotr32 $25, $10, 4 # dror32
  /external/llvm/test/MC/Mips/mips5/
invalid-mips64r2.s 16 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/test/MC/Mips/mips64/
invalid-mips64r2.s 17 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
mips64shift.ll 97 ; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22
  /external/llvm/test/MC/Mips/mips64r2/
invalid.s 37 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
38 drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
valid.s 98 drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe]
99 drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe]
  /external/llvm/test/MC/Mips/mips64r5/
invalid.s 11 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
12 drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
valid.s 98 drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe]
99 drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe]
  /external/swiftshader/third_party/LLVM/lib/Target/Mips/
Mips64InstrInfo.td 129 def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
  /art/runtime/interpreter/mterp/mips64/
header.S 252 drotr32 \reg, \reg, 0
  /external/llvm/lib/Target/Mips/
MicroMips64r6InstrInfo.td 61 class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
260 class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
  /external/llvm/test/MC/Disassembler/Mips/mips64r3/
valid-mips64r3-el.txt 124 0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
125 0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
  /external/llvm/test/MC/Disassembler/Mips/mips64r5/
valid-mips64r5-el.txt 124 0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
125 0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
  /external/llvm/test/MC/Mips/mips64r6/
invalid.s 68 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
69 drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate

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