| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86GenFastISel.inc | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Disassembler.cpp | 52 {0xff800000, 0x72800000, "movk <wd>, #<imm2>, lsl #<shift3>"},
53 {0xff800000, 0x52800000, "movz <wd>, #<imm2>, lsl #<shift3>"},
54 {0xff800000, 0xd2800000, "movz <xd>, #<imm2>, lsl #<shift3>"},
138 else if(strcmp(token, "<imm2>") == 0)
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ThumbDisassembler.c | 251 { "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2
253 { "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2
255 { "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2
333 { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
334 { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
335 { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
336 { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
337 { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
361 { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
362 { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| sp-pc-validations-bad-t.s | 241 @str.w pc,[r0,r1{,LSL #<imm2>}] @ Unpredictable
242 @str.w r1,[r0,sp{,LSL #<imm2>}] @ ditto
243 @str.w r1,[r0,pc{,LSL #<imm2>}] @ ditto
|
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1153 Instr Assembler::ImmBarrierDomain(int imm2) {
1154 DCHECK(is_uint2(imm2));
1155 return imm2 << ImmBarrierDomain_offset;
1159 Instr Assembler::ImmBarrierType(int imm2) {
1160 DCHECK(is_uint2(imm2));
1161 return imm2 << ImmBarrierType_offset;
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| xstormy16.cpu | 277 (dnf f-imm2 "2 bit unsigned" () 10 2)
278 (dnop imm2 "2 bit unsigned immediate" () h-uint f-imm2)
[all...] |
| /external/v8/src/wasm/ |
| wasm-module-builder.h | 133 void EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2);
|
| wasm-module-builder.cc | 121 const byte imm2) {
124 body_.push_back(imm2);
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| FastISel.h | 280 uint64_t Imm1, uint64_t Imm2);
308 uint64_t Imm1, uint64_t Imm2);
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetStreamer.h | 105 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
|
| Mips32r6InstrFormats.td | 493 bits<2> imm2;
502 let Inst{7-6} = imm2;
|
| MicroMips32r6InstrFormats.td | 412 bits<2> imm2;
420 let Inst{10-9} = imm2;
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| xstormy16-opc.c | 589 /* inc $Rd,#$imm2 */
592 { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } },
595 /* dec $Rd,#$imm2 */
598 { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } },
|
| xstormy16-desc.c | 277 { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
389 /* imm2: 2 bit unsigned immediate */
390 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
842 /* inc $Rd,#$imm2 */
847 /* dec $Rd,#$imm2 */
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonIntrinsics.td | 28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
29 : Pat<(IntID Imm1:$Is, Imm2:$It),
30 (MI Imm1:$Is, Imm2:$It)>;
62 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
63 : Pat <(IntID I32:$Rp, Imm1:$Is, Imm2:$It),
64 (MI (C2_tfrrp I32:$Rp), Imm1:$Is, Imm2:$It)>;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /art/compiler/linker/arm/ |
| relative_patcher_thumb2.cc | 298 __ Ldrb(ip, ldr_address); // Load the LDR (register) byte with "00 | imm2 | Rm",
299 // i.e. Rm+32 because the scale in imm2 is 2.
|
| relative_patcher_thumb2_test.cc | 64 // LDR register, lsl #2. Bits 4-5 are the imm2, i.e. the lsl shift.
664 0xeb000010 | // ADD Rd, Rn, Rm, LSR 32 (type=01, imm3=000, imm2=00)
[all...] |
| /external/vixl/test/aarch64/ |
| test-simulator-aarch64.cc | 172 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_peephole.cpp | 738 ImmediateValue &imm2)
740 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg;
837 const int s, ImmediateValue& imm2)
843 float f = imm2.reg.data.f32 * exp2f(mul2->postFactor);
859 // d = mul a, imm2 -> d = mul r, (imm1 * imm2)
901 ConstantFolding::opnd3(Instruction *i, ImmediateValue &imm2)
906 if (imm2.isInteger(0)) {
914 if (imm2.isInteger(0)) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/valgrind/none/tests/ppc32/ |
| test_dfp5.c | 239 typedef void (*test_funcp_t)(unsigned int imm, unsigned int imm2, dfp_val_t *valB);
|
| /external/valgrind/none/tests/ppc64/ |
| test_dfp5.c | 239 typedef void (*test_funcp_t)(unsigned int imm, unsigned int imm2, dfp_val_t *valB);
|
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_32.c | 1182 sljit_uw imm2; local
[all...] |
