1 //===-- FastISel.h - Definition of the FastISel class ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the FastISel class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_FASTISEL_H 15 #define LLVM_CODEGEN_FASTISEL_H 16 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/CodeGen/ValueTypes.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 21 namespace llvm { 22 23 class AllocaInst; 24 class ConstantFP; 25 class FunctionLoweringInfo; 26 class Instruction; 27 class MachineBasicBlock; 28 class MachineConstantPool; 29 class MachineFunction; 30 class MachineInstr; 31 class MachineFrameInfo; 32 class MachineRegisterInfo; 33 class TargetData; 34 class TargetInstrInfo; 35 class TargetLowering; 36 class TargetMachine; 37 class TargetRegisterClass; 38 class TargetRegisterInfo; 39 class LoadInst; 40 41 /// FastISel - This is a fast-path instruction selection class that 42 /// generates poor code and doesn't support illegal types or non-trivial 43 /// lowering, but runs quickly. 44 class FastISel { 45 protected: 46 DenseMap<const Value *, unsigned> LocalValueMap; 47 FunctionLoweringInfo &FuncInfo; 48 MachineRegisterInfo &MRI; 49 MachineFrameInfo &MFI; 50 MachineConstantPool &MCP; 51 DebugLoc DL; 52 const TargetMachine &TM; 53 const TargetData &TD; 54 const TargetInstrInfo &TII; 55 const TargetLowering &TLI; 56 const TargetRegisterInfo &TRI; 57 58 /// The position of the last instruction for materializing constants 59 /// for use in the current block. It resets to EmitStartPt when it 60 /// makes sense (for example, it's usually profitable to avoid function 61 /// calls between the definition and the use) 62 MachineInstr *LastLocalValue; 63 64 /// The top most instruction in the current block that is allowed for 65 /// emitting local variables. LastLocalValue resets to EmitStartPt when 66 /// it makes sense (for example, on function calls) 67 MachineInstr *EmitStartPt; 68 69 public: 70 /// getLastLocalValue - Return the position of the last instruction 71 /// emitted for materializing constants for use in the current block. 72 MachineInstr *getLastLocalValue() { return LastLocalValue; } 73 74 /// setLastLocalValue - Update the position of the last instruction 75 /// emitted for materializing constants for use in the current block. 76 void setLastLocalValue(MachineInstr *I) { 77 EmitStartPt = I; 78 LastLocalValue = I; 79 } 80 81 /// startNewBlock - Set the current block to which generated machine 82 /// instructions will be appended, and clear the local CSE map. 83 /// 84 void startNewBlock(); 85 86 /// getCurDebugLoc() - Return current debug location information. 87 DebugLoc getCurDebugLoc() const { return DL; } 88 89 /// SelectInstruction - Do "fast" instruction selection for the given 90 /// LLVM IR instruction, and append generated machine instructions to 91 /// the current block. Return true if selection was successful. 92 /// 93 bool SelectInstruction(const Instruction *I); 94 95 /// SelectOperator - Do "fast" instruction selection for the given 96 /// LLVM IR operator (Instruction or ConstantExpr), and append 97 /// generated machine instructions to the current block. Return true 98 /// if selection was successful. 99 /// 100 bool SelectOperator(const User *I, unsigned Opcode); 101 102 /// getRegForValue - Create a virtual register and arrange for it to 103 /// be assigned the value for the given LLVM value. 104 unsigned getRegForValue(const Value *V); 105 106 /// lookUpRegForValue - Look up the value to see if its value is already 107 /// cached in a register. It may be defined by instructions across blocks or 108 /// defined locally. 109 unsigned lookUpRegForValue(const Value *V); 110 111 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also 112 /// takes care of truncating or sign-extending the given getelementptr 113 /// index value. 114 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V); 115 116 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that 117 /// vreg is being provided by the specified load instruction. If possible, 118 /// try to fold the load as an operand to the instruction, returning true if 119 /// possible. 120 virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/, 121 const LoadInst * /*LI*/) { 122 return false; 123 } 124 125 /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions 126 /// into the current block. 127 void recomputeInsertPt(); 128 129 struct SavePoint { 130 MachineBasicBlock::iterator InsertPt; 131 DebugLoc DL; 132 }; 133 134 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions 135 /// into the local value area and return the old insert position. 136 SavePoint enterLocalValueArea(); 137 138 /// leaveLocalValueArea - Reset InsertPt to the given old insert position. 139 void leaveLocalValueArea(SavePoint Old); 140 141 virtual ~FastISel(); 142 143 protected: 144 explicit FastISel(FunctionLoweringInfo &funcInfo); 145 146 /// TargetSelectInstruction - This method is called by target-independent 147 /// code when the normal FastISel process fails to select an instruction. 148 /// This gives targets a chance to emit code for anything that doesn't 149 /// fit into FastISel's framework. It returns true if it was successful. 150 /// 151 virtual bool 152 TargetSelectInstruction(const Instruction *I) = 0; 153 154 /// FastEmit_r - This method is called by target-independent code 155 /// to request that an instruction with the given type and opcode 156 /// be emitted. 157 virtual unsigned FastEmit_(MVT VT, 158 MVT RetVT, 159 unsigned Opcode); 160 161 /// FastEmit_r - This method is called by target-independent code 162 /// to request that an instruction with the given type, opcode, and 163 /// register operand be emitted. 164 /// 165 virtual unsigned FastEmit_r(MVT VT, 166 MVT RetVT, 167 unsigned Opcode, 168 unsigned Op0, bool Op0IsKill); 169 170 /// FastEmit_rr - This method is called by target-independent code 171 /// to request that an instruction with the given type, opcode, and 172 /// register operands be emitted. 173 /// 174 virtual unsigned FastEmit_rr(MVT VT, 175 MVT RetVT, 176 unsigned Opcode, 177 unsigned Op0, bool Op0IsKill, 178 unsigned Op1, bool Op1IsKill); 179 180 /// FastEmit_ri - This method is called by target-independent code 181 /// to request that an instruction with the given type, opcode, and 182 /// register and immediate operands be emitted. 183 /// 184 virtual unsigned FastEmit_ri(MVT VT, 185 MVT RetVT, 186 unsigned Opcode, 187 unsigned Op0, bool Op0IsKill, 188 uint64_t Imm); 189 190 /// FastEmit_rf - This method is called by target-independent code 191 /// to request that an instruction with the given type, opcode, and 192 /// register and floating-point immediate operands be emitted. 193 /// 194 virtual unsigned FastEmit_rf(MVT VT, 195 MVT RetVT, 196 unsigned Opcode, 197 unsigned Op0, bool Op0IsKill, 198 const ConstantFP *FPImm); 199 200 /// FastEmit_rri - This method is called by target-independent code 201 /// to request that an instruction with the given type, opcode, and 202 /// register and immediate operands be emitted. 203 /// 204 virtual unsigned FastEmit_rri(MVT VT, 205 MVT RetVT, 206 unsigned Opcode, 207 unsigned Op0, bool Op0IsKill, 208 unsigned Op1, bool Op1IsKill, 209 uint64_t Imm); 210 211 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 212 /// to emit an instruction with an immediate operand using FastEmit_ri. 213 /// If that fails, it materializes the immediate into a register and try 214 /// FastEmit_rr instead. 215 unsigned FastEmit_ri_(MVT VT, 216 unsigned Opcode, 217 unsigned Op0, bool Op0IsKill, 218 uint64_t Imm, MVT ImmType); 219 220 /// FastEmit_i - This method is called by target-independent code 221 /// to request that an instruction with the given type, opcode, and 222 /// immediate operand be emitted. 223 virtual unsigned FastEmit_i(MVT VT, 224 MVT RetVT, 225 unsigned Opcode, 226 uint64_t Imm); 227 228 /// FastEmit_f - This method is called by target-independent code 229 /// to request that an instruction with the given type, opcode, and 230 /// floating-point immediate operand be emitted. 231 virtual unsigned FastEmit_f(MVT VT, 232 MVT RetVT, 233 unsigned Opcode, 234 const ConstantFP *FPImm); 235 236 /// FastEmitInst_ - Emit a MachineInstr with no operands and a 237 /// result register in the given register class. 238 /// 239 unsigned FastEmitInst_(unsigned MachineInstOpcode, 240 const TargetRegisterClass *RC); 241 242 /// FastEmitInst_r - Emit a MachineInstr with one register operand 243 /// and a result register in the given register class. 244 /// 245 unsigned FastEmitInst_r(unsigned MachineInstOpcode, 246 const TargetRegisterClass *RC, 247 unsigned Op0, bool Op0IsKill); 248 249 /// FastEmitInst_rr - Emit a MachineInstr with two register operands 250 /// and a result register in the given register class. 251 /// 252 unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 253 const TargetRegisterClass *RC, 254 unsigned Op0, bool Op0IsKill, 255 unsigned Op1, bool Op1IsKill); 256 257 /// FastEmitInst_rrr - Emit a MachineInstr with three register operands 258 /// and a result register in the given register class. 259 /// 260 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, 261 const TargetRegisterClass *RC, 262 unsigned Op0, bool Op0IsKill, 263 unsigned Op1, bool Op1IsKill, 264 unsigned Op2, bool Op2IsKill); 265 266 /// FastEmitInst_ri - Emit a MachineInstr with a register operand, 267 /// an immediate, and a result register in the given register class. 268 /// 269 unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 270 const TargetRegisterClass *RC, 271 unsigned Op0, bool Op0IsKill, 272 uint64_t Imm); 273 274 /// FastEmitInst_rii - Emit a MachineInstr with one register operand 275 /// and two immediate operands. 276 /// 277 unsigned FastEmitInst_rii(unsigned MachineInstOpcode, 278 const TargetRegisterClass *RC, 279 unsigned Op0, bool Op0IsKill, 280 uint64_t Imm1, uint64_t Imm2); 281 282 /// FastEmitInst_rf - Emit a MachineInstr with two register operands 283 /// and a result register in the given register class. 284 /// 285 unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 286 const TargetRegisterClass *RC, 287 unsigned Op0, bool Op0IsKill, 288 const ConstantFP *FPImm); 289 290 /// FastEmitInst_rri - Emit a MachineInstr with two register operands, 291 /// an immediate, and a result register in the given register class. 292 /// 293 unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 294 const TargetRegisterClass *RC, 295 unsigned Op0, bool Op0IsKill, 296 unsigned Op1, bool Op1IsKill, 297 uint64_t Imm); 298 299 /// FastEmitInst_i - Emit a MachineInstr with a single immediate 300 /// operand, and a result register in the given register class. 301 unsigned FastEmitInst_i(unsigned MachineInstrOpcode, 302 const TargetRegisterClass *RC, 303 uint64_t Imm); 304 305 /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands. 306 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode, 307 const TargetRegisterClass *RC, 308 uint64_t Imm1, uint64_t Imm2); 309 310 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg 311 /// from a specified index of a superregister to a specified type. 312 unsigned FastEmitInst_extractsubreg(MVT RetVT, 313 unsigned Op0, bool Op0IsKill, 314 uint32_t Idx); 315 316 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 317 /// with all but the least significant bit set to zero. 318 unsigned FastEmitZExtFromI1(MVT VT, 319 unsigned Op0, bool Op0IsKill); 320 321 /// FastEmitBranch - Emit an unconditional branch to the given block, 322 /// unless it is the immediate (fall-through) successor, and update 323 /// the CFG. 324 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); 325 326 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1); 327 328 unsigned createResultReg(const TargetRegisterClass *RC); 329 330 /// TargetMaterializeConstant - Emit a constant in a register using 331 /// target-specific logic, such as constant pool loads. 332 virtual unsigned TargetMaterializeConstant(const Constant* C) { 333 return 0; 334 } 335 336 /// TargetMaterializeAlloca - Emit an alloca address in a register using 337 /// target-specific logic. 338 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) { 339 return 0; 340 } 341 342 virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) { 343 return 0; 344 } 345 346 private: 347 bool SelectBinaryOp(const User *I, unsigned ISDOpcode); 348 349 bool SelectFNeg(const User *I); 350 351 bool SelectGetElementPtr(const User *I); 352 353 bool SelectCall(const User *I); 354 355 bool SelectBitCast(const User *I); 356 357 bool SelectCast(const User *I, unsigned Opcode); 358 359 bool SelectExtractValue(const User *I); 360 361 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 362 /// Emit code to ensure constants are copied into registers when needed. 363 /// Remember the virtual registers that need to be added to the Machine PHI 364 /// nodes as input. We cannot just directly add them, because expansion 365 /// might result in multiple MBB's for one BB. As such, the start of the 366 /// BB might correspond to a different MBB than the end. 367 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 368 369 /// materializeRegForValue - Helper for getRegForVale. This function is 370 /// called when the value isn't already available in a register and must 371 /// be materialized with new instructions. 372 unsigned materializeRegForValue(const Value *V, MVT VT); 373 374 /// flushLocalValueMap - clears LocalValueMap and moves the area for the 375 /// new local variables to the beginning of the block. It helps to avoid 376 /// spilling cached variables across heavy instructions like calls. 377 void flushLocalValueMap(); 378 379 /// hasTrivialKill - Test whether the given value has exactly one use. 380 bool hasTrivialKill(const Value *V) const; 381 }; 382 383 } 384 385 #endif 386
