| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-nios2/ |
| imm5_symbol.s | 1 .global imm5
3 .byte imm5
4 .set imm5, 31
|
| imm5.s | 1 # Test the imm5 relocation
7 roli r1, r1, imm5
|
| imm5.d | 2 #source: imm5.s
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-nds32/ |
| imm_symbol.s | 3 .globl imm5
7 .set imm5, 0xf
|
| imm.s | 6 la $r0, imm5
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/ |
| syscontrol_32.s | 10 /* sdbbp Imm5 -> sdbbp! Imm5 */
|
| shift_32.s | 24 /* slli/srli rD,rA,Imm5 -> slli!/srli! rD,Imm5 */
|
| load_store_32.s | 32 /* lw/sw rD,[rA,SImm15] -> lw!/sw! rD,[rA,Imm5] */
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| d30v-opc.c | 364 #define IMM5 (Ab + 1)
366 #define IMM5U (IMM5 + 1)
457 { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
459 { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
470 { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
471 { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
|
| v850-opc.c | 1125 /* The imm5 field in a format 2 insn. */
1129 /* The imm5 field in a format 11 insn. */
1139 /* The unsigned imm5 field in a format 2 insn. */
1143 /* The imm5 field in a prepare/dispose instruction. */
1144 #define IMM5 (I5U + 1)
1148 #define D5_4U (IMM5 + 1)
[all...] |
| cr16-opc.c | 148 SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr),
158 SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
558 {5, arg_ic, OP_SIGNED}, /* imm5 */
|
| v850-dis.c | 710 else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16<<16 */
716 else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16 */
722 else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm32 */
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrThumb.td | 214 // t_addrmode_is4 := reg + imm5 * 4
226 // t_addrmode_is2 := reg + imm5 * 2
238 // t_addrmode_is1 := reg + imm5
658 // Loads: reg/reg and reg/imm5
668 def i : // reg/imm5
680 // Stores: reg/reg and reg/imm5
686 def i : // reg/imm5
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrThumb.td | 168 // t_addrmode_is4 := reg + imm5 * 4
180 // t_addrmode_is2 := reg + imm5 * 2
192 // t_addrmode_is1 := reg + imm5
575 // Loads: reg/reg and reg/imm5
587 def i : // reg/imm5
593 // Stores: reg/reg and reg/imm5
604 def i : // reg/imm5
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_T2_32.c | 76 #define IMM5(imm) \
652 return push_inst32(compiler, LSL_WI | (flags & SET_FLAGS) | RD4(dst) | RM4(reg) | IMM5(imm));
656 return push_inst32(compiler, LSR_WI | (flags & SET_FLAGS) | RD4(dst) | RM4(reg) | IMM5(imm));
660 return push_inst32(compiler, ASR_WI | (flags & SET_FLAGS) | RD4(dst) | RM4(reg) | IMM5(imm));
834 /* w u l */ 0x6800 /* ldr imm5 */,
835 /* w u s */ 0x6000 /* str imm5 */,
836 /* w s l */ 0x6800 /* ldr imm5 */,
837 /* w s s */ 0x6000 /* str imm5 */,
839 /* b u l */ 0x7800 /* ldrb imm5 */,
840 /* b u s */ 0x7000 /* strb imm5 */,
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | 3200 UInt imm5 = INSN(20,16); local
8911 UInt imm5 = INSN(20,16); local
9349 UInt imm5 = INSN(20,16); local
13952 UInt imm5 = INSN(9,5); local
[all...] |
| guest_arm_toIR.c | 9128 UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; local
9188 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local
9246 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local
15952 UInt imm5 = INSN(11,7); local
16580 UInt imm5 = (insn >> 7) & 0x1F; \/* 11:7 *\/ local
18285 UInt imm5 = INSN(11,7); local
18340 UInt imm5 = INSN(11,7); local
18561 UInt imm5 = INSN(11,7); local
18665 UInt imm5 = INSN(11,7); local
20390 UInt imm5 = INSN0(10,6); local
20415 UInt imm5 = INSN0(10,6); local
20440 UInt imm5 = INSN0(10,6); local
20582 UInt imm5 = INSN0(10,6); local
21146 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
21226 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
21308 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
21399 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
21440 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
21480 UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); local
[all...] |
| host_arm_defs.h | 262 /* --------- Reg or imm5 operands --------- */
265 ARMri5_I5=9, /* imm5, 1 .. 31 only (no zero!) */
275 UInt imm5; member in struct:__anon36590::__anon36591::__anon36592
284 extern ARMRI5* ARMRI5_I5 ( UInt imm5 );
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| nds32.h | 114 #define N16_TYPE5(op10, imm5) \
115 (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
122 #define N16_TYPE25(op8, re, imm5) \
124 | __MF (imm5, 0, 5))
|
| h8300.h | 123 IMM5 = IMM | L_5,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeInstrFormats.td | 167 bits<5> imm5;
174 let Inst{27-31} = imm5;
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.cpp | 310 // Value=000000000000000000000iiiii0000000 where iiii defines the Imm5 value
332 // Encodes iiiiitt0mmmm for data-processing (2nd) operands where iiiii=Imm5,
335 IOffsetT imm5) {
337 assert(imm5 < (1 << kShiftImmBits));
338 return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
400 uint32_t Imm5;
402 Imm5 = ShAmt->getShAmtImm();
407 Imm5 = static_cast<uint32_t>(Val);
410 Value = encodeShiftRotateImm5(Rm, FlexReg->getShiftOp(), Imm5);
821 constexpr IValueT Imm5 = 0
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| bfin-parse.y | 212 #define imm5(x) EXPR_VALUE (x)
[all...] |
