1 /* bfin-parse.y ADI Blackfin parser 2 Copyright (C) 2005-2014 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 %{ 21 22 #include "as.h" 23 24 #include "bfin-aux.h" /* Opcode generating auxiliaries. */ 25 #include "libbfd.h" 26 #include "elf/common.h" 27 #include "elf/bfin.h" 28 29 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \ 30 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1) 31 32 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ 33 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \ 34 dst, src0, src1, w0) 35 36 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ 37 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \ 38 dst, src0, src1, w0) 39 40 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \ 41 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls) 42 43 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \ 44 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls) 45 46 #define LDIMMHALF_R(reg, h, s, z, hword) \ 47 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1) 48 49 #define LDIMMHALF_R5(reg, h, s, z, hword) \ 50 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2) 51 52 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \ 53 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset) 54 55 #define LDST(ptr, reg, aop, sz, z, w) \ 56 bfin_gen_ldst (ptr, reg, aop, sz, z, w) 57 58 #define LDSTII(ptr, reg, offset, w, op) \ 59 bfin_gen_ldstii (ptr, reg, offset, w, op) 60 61 #define DSPLDST(i, m, reg, aop, w) \ 62 bfin_gen_dspldst (i, reg, aop, w, m) 63 64 #define LDSTPMOD(ptr, reg, idx, aop, w) \ 65 bfin_gen_ldstpmod (ptr, reg, aop, w, idx) 66 67 #define LDSTIIFP(offset, reg, w) \ 68 bfin_gen_ldstiifp (reg, offset, w) 69 70 #define LOGI2OP(dst, src, opc) \ 71 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK) 72 73 #define ALU2OP(dst, src, opc) \ 74 bfin_gen_alu2op (dst, src, opc) 75 76 #define BRCC(t, b, offset) \ 77 bfin_gen_brcc (t, b, offset) 78 79 #define UJUMP(offset) \ 80 bfin_gen_ujump (offset) 81 82 #define PROGCTRL(prgfunc, poprnd) \ 83 bfin_gen_progctrl (prgfunc, poprnd) 84 85 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \ 86 bfin_gen_pushpopmultiple (dr, pr, d, p, w) 87 88 #define PUSHPOPREG(reg, w) \ 89 bfin_gen_pushpopreg (reg, w) 90 91 #define CALLA(addr, s) \ 92 bfin_gen_calla (addr, s) 93 94 #define LINKAGE(r, framesize) \ 95 bfin_gen_linkage (r, framesize) 96 97 #define COMPI2OPD(dst, src, op) \ 98 bfin_gen_compi2opd (dst, src, op) 99 100 #define COMPI2OPP(dst, src, op) \ 101 bfin_gen_compi2opp (dst, src, op) 102 103 #define DAGMODIK(i, op) \ 104 bfin_gen_dagmodik (i, op) 105 106 #define DAGMODIM(i, m, op, br) \ 107 bfin_gen_dagmodim (i, m, op, br) 108 109 #define COMP3OP(dst, src0, src1, opc) \ 110 bfin_gen_comp3op (src0, src1, dst, opc) 111 112 #define PTR2OP(dst, src, opc) \ 113 bfin_gen_ptr2op (dst, src, opc) 114 115 #define CCFLAG(x, y, opc, i, g) \ 116 bfin_gen_ccflag (x, y, opc, i, g) 117 118 #define CCMV(src, dst, t) \ 119 bfin_gen_ccmv (src, dst, t) 120 121 #define CACTRL(reg, a, op) \ 122 bfin_gen_cactrl (reg, a, op) 123 124 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \ 125 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg) 126 127 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0)) 128 #define IS_RANGE(bits, expr, sign, mul) \ 129 value_match(expr, bits, sign, mul, 1) 130 #define IS_URANGE(bits, expr, sign, mul) \ 131 value_match(expr, bits, sign, mul, 0) 132 #define IS_CONST(expr) (expr->type == Expr_Node_Constant) 133 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant) 134 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1) 135 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0) 136 137 #define IS_PCREL4(expr) \ 138 (value_match (expr, 4, 0, 2, 0)) 139 140 #define IS_LPPCREL10(expr) \ 141 (value_match (expr, 10, 0, 2, 0)) 142 143 #define IS_PCREL10(expr) \ 144 (value_match (expr, 10, 0, 2, 1)) 145 146 #define IS_PCREL12(expr) \ 147 (value_match (expr, 12, 0, 2, 1)) 148 149 #define IS_PCREL24(expr) \ 150 (value_match (expr, 24, 0, 2, 1)) 151 152 153 static int value_match (Expr_Node *, int, int, int, int); 154 155 extern FILE *errorf; 156 extern INSTR_T insn; 157 158 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *); 159 static Expr_Node *unary (Expr_Op_Type, Expr_Node *); 160 161 static void notethat (char *, ...); 162 163 char *current_inputline; 164 extern char *yytext; 165 int yyerror (char *); 166 167 /* Used to set SRCx fields to all 1s as described in the PRM. */ 168 static Register reg7 = {REG_R7, 0}; 169 170 void error (char *format, ...) 171 { 172 va_list ap; 173 static char buffer[2000]; 174 175 va_start (ap, format); 176 vsprintf (buffer, format, ap); 177 va_end (ap); 178 179 as_bad ("%s", buffer); 180 } 181 182 int 183 yyerror (char *msg) 184 { 185 if (msg[0] == '\0') 186 error ("%s", msg); 187 188 else if (yytext[0] != ';') 189 error ("%s. Input text was %s.", msg, yytext); 190 else 191 error ("%s.", msg); 192 193 return -1; 194 } 195 196 static int 197 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask) 198 { 199 int val = EXPR_VALUE (exp); 200 if (exp->type != Expr_Node_Constant) 201 return 0; 202 if (val < from || val > to) 203 return 0; 204 return (val & mask) == 0; 205 } 206 207 extern int yylex (void); 208 209 #define imm3(x) EXPR_VALUE (x) 210 #define imm4(x) EXPR_VALUE (x) 211 #define uimm4(x) EXPR_VALUE (x) 212 #define imm5(x) EXPR_VALUE (x) 213 #define uimm5(x) EXPR_VALUE (x) 214 #define imm6(x) EXPR_VALUE (x) 215 #define imm7(x) EXPR_VALUE (x) 216 #define uimm8(x) EXPR_VALUE (x) 217 #define imm16(x) EXPR_VALUE (x) 218 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2) 219 #define uimm16(x) EXPR_VALUE (x) 220 221 /* Return true if a value is inside a range. */ 222 #define IN_RANGE(x, low, high) \ 223 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high))) 224 225 /* Auxiliary functions. */ 226 227 static int 228 valid_dreg_pair (Register *reg1, Expr_Node *reg2) 229 { 230 if (!IS_DREG (*reg1)) 231 { 232 yyerror ("Dregs expected"); 233 return 0; 234 } 235 236 if (reg1->regno != 1 && reg1->regno != 3) 237 { 238 yyerror ("Bad register pair"); 239 return 0; 240 } 241 242 if (imm7 (reg2) != reg1->regno - 1) 243 { 244 yyerror ("Bad register pair"); 245 return 0; 246 } 247 248 reg1->regno--; 249 return 1; 250 } 251 252 static int 253 check_multiply_halfregs (Macfunc *aa, Macfunc *ab) 254 { 255 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1)) 256 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0))) 257 return yyerror ("Source multiplication register mismatch"); 258 259 return 0; 260 } 261 262 263 /* Check mac option. */ 264 265 static int 266 check_macfunc_option (Macfunc *a, Opt_mode *opt) 267 { 268 /* Default option is always valid. */ 269 if (opt->mod == 0) 270 return 0; 271 272 if ((a->w == 1 && a->P == 1 273 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU 274 && opt->mod != M_S2RND && opt->mod != M_ISS2) 275 || (a->w == 1 && a->P == 0 276 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU 277 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND 278 && opt->mod != M_ISS2 && opt->mod != M_IH) 279 || (a->w == 0 && a->P == 0 280 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32)) 281 return -1; 282 283 return 0; 284 } 285 286 /* Check (vector) mac funcs and ops. */ 287 288 static int 289 check_macfuncs (Macfunc *aa, Opt_mode *opa, 290 Macfunc *ab, Opt_mode *opb) 291 { 292 /* Variables for swapping. */ 293 Macfunc mtmp; 294 Opt_mode otmp; 295 296 /* The option mode should be put at the end of the second instruction 297 of the vector except M, which should follow MAC1 instruction. */ 298 if (opa->mod != 0) 299 return yyerror ("Bad opt mode"); 300 301 /* If a0macfunc comes before a1macfunc, swap them. */ 302 303 if (aa->n == 0) 304 { 305 /* (M) is not allowed here. */ 306 if (opa->MM != 0) 307 return yyerror ("(M) not allowed with A0MAC"); 308 if (ab->n != 1) 309 return yyerror ("Vector AxMACs can't be same"); 310 311 mtmp = *aa; *aa = *ab; *ab = mtmp; 312 otmp = *opa; *opa = *opb; *opb = otmp; 313 } 314 else 315 { 316 if (opb->MM != 0) 317 return yyerror ("(M) not allowed with A0MAC"); 318 if (ab->n != 0) 319 return yyerror ("Vector AxMACs can't be same"); 320 } 321 322 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both 323 assignment_or_macfuncs. */ 324 if ((aa->op == 0 || aa->op == 1 || aa->op == 2) 325 && (ab->op == 0 || ab->op == 1 || ab->op == 2)) 326 { 327 if (check_multiply_halfregs (aa, ab) < 0) 328 return -1; 329 } 330 else 331 { 332 /* Only one of the assign_macfuncs has a half reg multiply 333 Evil trick: Just 'OR' their source register codes: 334 We can do that, because we know they were initialized to 0 335 in the rules that don't use multiply_halfregs. */ 336 aa->s0.regno |= (ab->s0.regno & CODE_MASK); 337 aa->s1.regno |= (ab->s1.regno & CODE_MASK); 338 } 339 340 if (aa->w == ab->w && aa->P != ab->P) 341 return yyerror ("Destination Dreg sizes (full or half) must match"); 342 343 if (aa->w && ab->w) 344 { 345 if (aa->P && (aa->dst.regno - ab->dst.regno) != 1) 346 return yyerror ("Destination Dregs (full) must differ by one"); 347 if (!aa->P && aa->dst.regno != ab->dst.regno) 348 return yyerror ("Destination Dregs (half) must match"); 349 } 350 351 /* Make sure mod flags get ORed, too. */ 352 opb->mod |= opa->mod; 353 354 /* Check option. */ 355 if (check_macfunc_option (aa, opb) < 0 356 && check_macfunc_option (ab, opb) < 0) 357 return yyerror ("bad option"); 358 359 /* Make sure first macfunc has got both P flags ORed. */ 360 aa->P |= ab->P; 361 362 return 0; 363 } 364 365 366 static int 367 is_group1 (INSTR_T x) 368 { 369 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */ 370 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000)) 371 return 1; 372 373 return 0; 374 } 375 376 static int 377 is_group2 (INSTR_T x) 378 { 379 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */ 380 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */ 381 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */ 382 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */ 383 || (x->value == 0x0000)) 384 return 1; 385 return 0; 386 } 387 388 static int 389 is_store (INSTR_T x) 390 { 391 if (!x) 392 return 0; 393 394 if ((x->value & 0xf000) == 0x8000) 395 { 396 int aop = ((x->value >> 9) & 0x3); 397 int w = ((x->value >> 11) & 0x1); 398 if (!w || aop == 3) 399 return 0; 400 return 1; 401 } 402 403 if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */ 404 ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */ 405 return 0; 406 407 /* decode_dspLDST_0 */ 408 if ((x->value & 0xFC00) == 0x9C00) 409 { 410 int w = ((x->value >> 9) & 0x1); 411 if (w) 412 return 1; 413 } 414 415 return 0; 416 } 417 418 static INSTR_T 419 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2) 420 { 421 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0; 422 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0; 423 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0; 424 425 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3)) 426 yyerror ("resource conflict in multi-issue instruction"); 427 428 /* Anomaly 05000074 */ 429 if (ENABLE_AC_05000074 430 && dsp32 != NULL && dsp16_grp1 != NULL 431 && (dsp32->value & 0xf780) == 0xc680 432 && ((dsp16_grp1->value & 0xfe40) == 0x9240 433 || (dsp16_grp1->value & 0xfe08) == 0xba08 434 || (dsp16_grp1->value & 0xfc00) == 0xbc00)) 435 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \ 436 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported"); 437 438 if (is_store (dsp16_grp1) && is_store (dsp16_grp2)) 439 yyerror ("Only one instruction in multi-issue instruction can be a store"); 440 441 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2); 442 } 443 444 %} 445 446 %union { 447 INSTR_T instr; 448 Expr_Node *expr; 449 SYMBOL_T symbol; 450 long value; 451 Register reg; 452 Macfunc macfunc; 453 struct { int r0; int s0; int x0; int aop; } modcodes; 454 struct { int r0; } r0; 455 Opt_mode mod; 456 } 457 458 459 /* Tokens. */ 460 461 /* Vector Specific. */ 462 %token BYTEOP16P BYTEOP16M 463 %token BYTEOP1P BYTEOP2P BYTEOP3P 464 %token BYTEUNPACK BYTEPACK 465 %token PACK 466 %token SAA 467 %token ALIGN8 ALIGN16 ALIGN24 468 %token VIT_MAX 469 %token EXTRACT DEPOSIT EXPADJ SEARCH 470 %token ONES SIGN SIGNBITS 471 472 /* Stack. */ 473 %token LINK UNLINK 474 475 /* Registers. */ 476 %token REG 477 %token PC 478 %token CCREG BYTE_DREG 479 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE 480 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H 481 %token HALF_REG 482 483 /* Progctrl. */ 484 %token NOP 485 %token RTI RTS RTX RTN RTE 486 %token HLT IDLE 487 %token STI CLI 488 %token CSYNC SSYNC 489 %token EMUEXCPT 490 %token RAISE EXCPT 491 %token LSETUP 492 %token LOOP 493 %token LOOP_BEGIN 494 %token LOOP_END 495 %token DISALGNEXCPT 496 %token JUMP JUMP_DOT_S JUMP_DOT_L 497 %token CALL 498 499 /* Emulator only. */ 500 %token ABORT 501 502 /* Operators. */ 503 %token NOT TILDA BANG 504 %token AMPERSAND BAR 505 %token PERCENT 506 %token CARET 507 %token BXOR 508 509 %token MINUS PLUS STAR SLASH 510 %token NEG 511 %token MIN MAX ABS 512 %token DOUBLE_BAR 513 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS 514 %token _MINUS_MINUS _PLUS_PLUS 515 516 /* Shift/rotate ops. */ 517 %token SHIFT LSHIFT ASHIFT BXORSHIFT 518 %token _GREATER_GREATER_GREATER_THAN_ASSIGN 519 %token ROT 520 %token LESS_LESS GREATER_GREATER 521 %token _GREATER_GREATER_GREATER 522 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN 523 %token DIVS DIVQ 524 525 /* In place operators. */ 526 %token ASSIGN _STAR_ASSIGN 527 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN 528 %token _MINUS_ASSIGN _PLUS_ASSIGN 529 530 /* Assignments, comparisons. */ 531 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN 532 %token GE LT LE GT 533 %token LESS_THAN 534 535 /* Cache. */ 536 %token FLUSHINV FLUSH 537 %token IFLUSH PREFETCH 538 539 /* Misc. */ 540 %token PRNT 541 %token OUTC 542 %token WHATREG 543 %token TESTSET 544 545 /* Modifiers. */ 546 %token ASL ASR 547 %token B W 548 %token NS S CO SCO 549 %token TH TL 550 %token BP 551 %token BREV 552 %token X Z 553 %token M MMOD 554 %token R RND RNDL RNDH RND12 RND20 555 %token V 556 %token LO HI 557 558 /* Bit ops. */ 559 %token BITTGL BITCLR BITSET BITTST BITMUX 560 561 /* Debug. */ 562 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX 563 564 /* Semantic auxiliaries. */ 565 566 %token IF COMMA BY 567 %token COLON SEMICOLON 568 %token RPAREN LPAREN LBRACK RBRACK 569 %token STATUS_REG 570 %token MNOP 571 %token SYMBOL NUMBER 572 %token GOT GOT17M4 FUNCDESC_GOT17M4 573 %token AT PLTPC 574 575 /* Types. */ 576 %type <instr> asm 577 %type <value> MMOD 578 %type <mod> opt_mode 579 580 %type <value> NUMBER 581 %type <r0> aligndir 582 %type <modcodes> byteop_mod 583 %type <reg> a_assign 584 %type <reg> a_plusassign 585 %type <reg> a_minusassign 586 %type <macfunc> multiply_halfregs 587 %type <macfunc> assign_macfunc 588 %type <macfunc> a_macfunc 589 %type <expr> expr_1 590 %type <instr> asm_1 591 %type <r0> vmod 592 %type <modcodes> vsmod 593 %type <modcodes> ccstat 594 %type <r0> cc_op 595 %type <reg> CCREG 596 %type <reg> reg_with_postinc 597 %type <reg> reg_with_predec 598 599 %type <r0> searchmod 600 %type <expr> symbol 601 %type <symbol> SYMBOL 602 %type <expr> eterm 603 %type <reg> REG 604 %type <reg> BYTE_DREG 605 %type <reg> REG_A_DOUBLE_ZERO 606 %type <reg> REG_A_DOUBLE_ONE 607 %type <reg> REG_A 608 %type <reg> STATUS_REG 609 %type <expr> expr 610 %type <r0> xpmod 611 %type <r0> xpmod1 612 %type <modcodes> smod 613 %type <modcodes> b3_op 614 %type <modcodes> rnd_op 615 %type <modcodes> post_op 616 %type <reg> HALF_REG 617 %type <r0> iu_or_nothing 618 %type <r0> plus_minus 619 %type <r0> asr_asl 620 %type <r0> asr_asl_0 621 %type <modcodes> sco 622 %type <modcodes> amod0 623 %type <modcodes> amod1 624 %type <modcodes> amod2 625 %type <r0> op_bar_op 626 %type <r0> w32_or_nothing 627 %type <r0> c_align 628 %type <r0> min_max 629 %type <expr> got 630 %type <expr> got_or_expr 631 %type <expr> pltpc 632 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4 633 634 /* Precedence rules. */ 635 %left BAR 636 %left CARET 637 %left AMPERSAND 638 %left LESS_LESS GREATER_GREATER 639 %left PLUS MINUS 640 %left STAR SLASH PERCENT 641 642 %right ASSIGN 643 644 %right TILDA BANG 645 %start statement 646 %% 647 statement: 648 | asm 649 { 650 insn = $1; 651 if (insn == (INSTR_T) 0) 652 return NO_INSN_GENERATED; 653 else if (insn == (INSTR_T) - 1) 654 return SEMANTIC_ERROR; 655 else 656 return INSN_GENERATED; 657 } 658 ; 659 660 asm: asm_1 SEMICOLON 661 /* Parallel instructions. */ 662 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON 663 { 664 if (($1->value & 0xf800) == 0xc000) 665 { 666 if (is_group1 ($3) && is_group2 ($5)) 667 $$ = gen_multi_instr_1 ($1, $3, $5); 668 else if (is_group2 ($3) && is_group1 ($5)) 669 $$ = gen_multi_instr_1 ($1, $5, $3); 670 else 671 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group"); 672 } 673 else if (($3->value & 0xf800) == 0xc000) 674 { 675 if (is_group1 ($1) && is_group2 ($5)) 676 $$ = gen_multi_instr_1 ($3, $1, $5); 677 else if (is_group2 ($1) && is_group1 ($5)) 678 $$ = gen_multi_instr_1 ($3, $5, $1); 679 else 680 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group"); 681 } 682 else if (($5->value & 0xf800) == 0xc000) 683 { 684 if (is_group1 ($1) && is_group2 ($3)) 685 $$ = gen_multi_instr_1 ($5, $1, $3); 686 else if (is_group2 ($1) && is_group1 ($3)) 687 $$ = gen_multi_instr_1 ($5, $3, $1); 688 else 689 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group"); 690 } 691 else 692 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n"); 693 } 694 695 | asm_1 DOUBLE_BAR asm_1 SEMICOLON 696 { 697 if (($1->value & 0xf800) == 0xc000) 698 { 699 if (is_group1 ($3)) 700 $$ = gen_multi_instr_1 ($1, $3, 0); 701 else if (is_group2 ($3)) 702 $$ = gen_multi_instr_1 ($1, 0, $3); 703 else 704 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group"); 705 } 706 else if (($3->value & 0xf800) == 0xc000) 707 { 708 if (is_group1 ($1)) 709 $$ = gen_multi_instr_1 ($3, $1, 0); 710 else if (is_group2 ($1)) 711 $$ = gen_multi_instr_1 ($3, 0, $1); 712 else 713 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group"); 714 } 715 else if (is_group1 ($1) && is_group2 ($3)) 716 $$ = gen_multi_instr_1 (0, $1, $3); 717 else if (is_group2 ($1) && is_group1 ($3)) 718 $$ = gen_multi_instr_1 (0, $3, $1); 719 else 720 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group"); 721 } 722 | error 723 { 724 $$ = 0; 725 yyerror (""); 726 yyerrok; 727 } 728 ; 729 730 /* DSPMAC. */ 731 732 asm_1: 733 MNOP 734 { 735 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0); 736 } 737 | assign_macfunc opt_mode 738 { 739 int op0, op1; 740 int w0 = 0, w1 = 0; 741 int h00, h10, h01, h11; 742 743 if (check_macfunc_option (&$1, &$2) < 0) 744 return yyerror ("bad option"); 745 746 if ($1.n == 0) 747 { 748 if ($2.MM) 749 return yyerror ("(m) not allowed with a0 unit"); 750 op1 = 3; 751 op0 = $1.op; 752 w1 = 0; 753 w0 = $1.w; 754 h00 = IS_H ($1.s0); 755 h10 = IS_H ($1.s1); 756 h01 = h11 = 0; 757 } 758 else 759 { 760 op1 = $1.op; 761 op0 = 3; 762 w1 = $1.w; 763 w0 = 0; 764 h00 = h10 = 0; 765 h01 = IS_H ($1.s0); 766 h11 = IS_H ($1.s1); 767 } 768 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10, 769 &$1.dst, op0, &$1.s0, &$1.s1, w0); 770 } 771 772 773 /* VECTOR MACs. */ 774 775 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode 776 { 777 Register *dst; 778 779 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0) 780 return -1; 781 notethat ("assign_macfunc (.), assign_macfunc (.)\n"); 782 783 if ($1.w) 784 dst = &$1.dst; 785 else 786 dst = &$4.dst; 787 788 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P, 789 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1), 790 dst, $4.op, &$1.s0, &$1.s1, $4.w); 791 } 792 793 /* DSPALU. */ 794 795 | DISALGNEXCPT 796 { 797 notethat ("dsp32alu: DISALGNEXCPT\n"); 798 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3); 799 } 800 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN 801 { 802 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5)) 803 { 804 notethat ("dsp32alu: dregs = ( A0 += A1 )\n"); 805 $$ = DSP32ALU (11, 0, 0, &$1, ®7, ®7, 0, 0, 0); 806 } 807 else 808 return yyerror ("Register mismatch"); 809 } 810 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN 811 { 812 if (!IS_A1 ($4) && IS_A1 ($5)) 813 { 814 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n"); 815 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, ®7, ®7, 0, 0, 1); 816 } 817 else 818 return yyerror ("Register mismatch"); 819 } 820 | A_ZERO_DOT_H ASSIGN HALF_REG 821 { 822 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n"); 823 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0); 824 } 825 | A_ONE_DOT_H ASSIGN HALF_REG 826 { 827 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n"); 828 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2); 829 } 830 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG 831 COLON expr COMMA REG COLON expr RPAREN aligndir 832 { 833 if (!IS_DREG ($2) || !IS_DREG ($4)) 834 return yyerror ("Dregs expected"); 835 else if (REG_SAME ($2, $4)) 836 return yyerror ("Illegal dest register combination"); 837 else if (!valid_dreg_pair (&$9, $11)) 838 return yyerror ("Bad dreg pair"); 839 else if (!valid_dreg_pair (&$13, $15)) 840 return yyerror ("Bad dreg pair"); 841 else 842 { 843 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n"); 844 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0); 845 } 846 } 847 848 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA 849 REG COLON expr RPAREN aligndir 850 { 851 if (!IS_DREG ($2) || !IS_DREG ($4)) 852 return yyerror ("Dregs expected"); 853 else if (REG_SAME ($2, $4)) 854 return yyerror ("Illegal dest register combination"); 855 else if (!valid_dreg_pair (&$9, $11)) 856 return yyerror ("Bad dreg pair"); 857 else if (!valid_dreg_pair (&$13, $15)) 858 return yyerror ("Bad dreg pair"); 859 else 860 { 861 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n"); 862 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1); 863 } 864 } 865 866 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir 867 { 868 if (!IS_DREG ($2) || !IS_DREG ($4)) 869 return yyerror ("Dregs expected"); 870 else if (REG_SAME ($2, $4)) 871 return yyerror ("Illegal dest register combination"); 872 else if (!valid_dreg_pair (&$8, $10)) 873 return yyerror ("Bad dreg pair"); 874 else 875 { 876 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n"); 877 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1); 878 } 879 } 880 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN 881 { 882 if (REG_SAME ($2, $4)) 883 return yyerror ("Illegal dest register combination"); 884 885 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8)) 886 { 887 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n"); 888 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0); 889 } 890 else 891 return yyerror ("Register mismatch"); 892 } 893 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA 894 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H 895 { 896 if (REG_SAME ($1, $7)) 897 return yyerror ("Illegal dest register combination"); 898 899 if (IS_DREG ($1) && IS_DREG ($7)) 900 { 901 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n"); 902 $$ = DSP32ALU (12, 0, &$1, &$7, ®7, ®7, 0, 0, 1); 903 } 904 else 905 return yyerror ("Register mismatch"); 906 } 907 908 909 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1 910 { 911 if (REG_SAME ($1, $7)) 912 return yyerror ("Resource conflict in dest reg"); 913 914 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5) 915 && IS_A1 ($9) && !IS_A1 ($11)) 916 { 917 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n"); 918 $$ = DSP32ALU (17, 0, &$1, &$7, ®7, ®7, $12.s0, $12.x0, 0); 919 920 } 921 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5) 922 && !IS_A1 ($9) && IS_A1 ($11)) 923 { 924 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n"); 925 $$ = DSP32ALU (17, 0, &$1, &$7, ®7, ®7, $12.s0, $12.x0, 1); 926 } 927 else 928 return yyerror ("Register mismatch"); 929 } 930 931 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1 932 { 933 if ($4.r0 == $10.r0) 934 return yyerror ("Operators must differ"); 935 936 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5) 937 && REG_SAME ($3, $9) && REG_SAME ($5, $11)) 938 { 939 notethat ("dsp32alu: dregs = dregs + dregs," 940 "dregs = dregs - dregs (amod1)\n"); 941 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2); 942 } 943 else 944 return yyerror ("Register mismatch"); 945 } 946 947 /* Bar Operations. */ 948 949 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2 950 { 951 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11)) 952 return yyerror ("Differing source registers"); 953 954 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7)) 955 return yyerror ("Dregs expected"); 956 957 if (REG_SAME ($1, $7)) 958 return yyerror ("Resource conflict in dest reg"); 959 960 if ($4.r0 == 1 && $10.r0 == 2) 961 { 962 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n"); 963 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0); 964 } 965 else if ($4.r0 == 0 && $10.r0 == 3) 966 { 967 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n"); 968 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0); 969 } 970 else 971 return yyerror ("Bar operand mismatch"); 972 } 973 974 | REG ASSIGN ABS REG vmod 975 { 976 int op; 977 978 if (IS_DREG ($1) && IS_DREG ($4)) 979 { 980 if ($5.r0) 981 { 982 notethat ("dsp32alu: dregs = ABS dregs (v)\n"); 983 op = 6; 984 } 985 else 986 { 987 /* Vector version of ABS. */ 988 notethat ("dsp32alu: dregs = ABS dregs\n"); 989 op = 7; 990 } 991 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2); 992 } 993 else 994 return yyerror ("Dregs expected"); 995 } 996 | a_assign ABS REG_A 997 { 998 notethat ("dsp32alu: Ax = ABS Ax\n"); 999 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, ®7, ®7, 0, 0, IS_A1 ($3)); 1000 } 1001 | A_ZERO_DOT_L ASSIGN HALF_REG 1002 { 1003 if (IS_DREG_L ($3)) 1004 { 1005 notethat ("dsp32alu: A0.l = reg_half\n"); 1006 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0); 1007 } 1008 else 1009 return yyerror ("A0.l = Rx.l expected"); 1010 } 1011 | A_ONE_DOT_L ASSIGN HALF_REG 1012 { 1013 if (IS_DREG_L ($3)) 1014 { 1015 notethat ("dsp32alu: A1.l = reg_half\n"); 1016 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2); 1017 } 1018 else 1019 return yyerror ("A1.l = Rx.l expected"); 1020 } 1021 1022 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN 1023 { 1024 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7)) 1025 { 1026 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n"); 1027 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0); 1028 } 1029 else 1030 return yyerror ("Dregs expected"); 1031 } 1032 1033 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod 1034 { 1035 if (!IS_DREG ($1)) 1036 return yyerror ("Dregs expected"); 1037 else if (!valid_dreg_pair (&$5, $7)) 1038 return yyerror ("Bad dreg pair"); 1039 else if (!valid_dreg_pair (&$9, $11)) 1040 return yyerror ("Bad dreg pair"); 1041 else 1042 { 1043 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n"); 1044 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0); 1045 } 1046 } 1047 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN 1048 { 1049 if (!IS_DREG ($1)) 1050 return yyerror ("Dregs expected"); 1051 else if (!valid_dreg_pair (&$5, $7)) 1052 return yyerror ("Bad dreg pair"); 1053 else if (!valid_dreg_pair (&$9, $11)) 1054 return yyerror ("Bad dreg pair"); 1055 else 1056 { 1057 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n"); 1058 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0); 1059 } 1060 } 1061 1062 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN 1063 rnd_op 1064 { 1065 if (!IS_DREG ($1)) 1066 return yyerror ("Dregs expected"); 1067 else if (!valid_dreg_pair (&$5, $7)) 1068 return yyerror ("Bad dreg pair"); 1069 else if (!valid_dreg_pair (&$9, $11)) 1070 return yyerror ("Bad dreg pair"); 1071 else 1072 { 1073 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n"); 1074 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop); 1075 } 1076 } 1077 1078 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN 1079 b3_op 1080 { 1081 if (!IS_DREG ($1)) 1082 return yyerror ("Dregs expected"); 1083 else if (!valid_dreg_pair (&$5, $7)) 1084 return yyerror ("Bad dreg pair"); 1085 else if (!valid_dreg_pair (&$9, $11)) 1086 return yyerror ("Bad dreg pair"); 1087 else 1088 { 1089 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n"); 1090 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0); 1091 } 1092 } 1093 1094 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN 1095 { 1096 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7)) 1097 { 1098 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n"); 1099 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0); 1100 } 1101 else 1102 return yyerror ("Dregs expected"); 1103 } 1104 1105 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR 1106 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG 1107 { 1108 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17)) 1109 { 1110 notethat ("dsp32alu: dregs_hi = dregs_lo =" 1111 "SIGN (dregs_hi) * dregs_hi + " 1112 "SIGN (dregs_lo) * dregs_lo \n"); 1113 1114 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0); 1115 } 1116 else 1117 return yyerror ("Dregs expected"); 1118 } 1119 | REG ASSIGN REG plus_minus REG amod1 1120 { 1121 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)) 1122 { 1123 if ($6.aop == 0) 1124 { 1125 /* No saturation flag specified, generate the 16 bit variant. */ 1126 notethat ("COMP3op: dregs = dregs +- dregs\n"); 1127 $$ = COMP3OP (&$1, &$3, &$5, $4.r0); 1128 } 1129 else 1130 { 1131 /* Saturation flag specified, generate the 32 bit variant. */ 1132 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n"); 1133 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0); 1134 } 1135 } 1136 else 1137 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0) 1138 { 1139 notethat ("COMP3op: pregs = pregs + pregs\n"); 1140 $$ = COMP3OP (&$1, &$3, &$5, 5); 1141 } 1142 else 1143 return yyerror ("Dregs expected"); 1144 } 1145 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod 1146 { 1147 int op; 1148 1149 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7)) 1150 { 1151 if ($9.r0) 1152 op = 6; 1153 else 1154 op = 7; 1155 1156 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n"); 1157 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0); 1158 } 1159 else 1160 return yyerror ("Dregs expected"); 1161 } 1162 1163 | a_assign MINUS REG_A 1164 { 1165 notethat ("dsp32alu: Ax = - Ax\n"); 1166 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, ®7, ®7, 0, 0, IS_A1 ($3)); 1167 } 1168 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1 1169 { 1170 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n"); 1171 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5, 1172 $6.s0, $6.x0, HL2 ($3, $5)); 1173 } 1174 | a_assign a_assign expr 1175 { 1176 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2)) 1177 { 1178 notethat ("dsp32alu: A1 = A0 = 0\n"); 1179 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 0, 0, 2); 1180 } 1181 else 1182 return yyerror ("Bad value, 0 expected"); 1183 } 1184 1185 /* Saturating. */ 1186 | a_assign REG_A LPAREN S RPAREN 1187 { 1188 if (REG_SAME ($1, $2)) 1189 { 1190 notethat ("dsp32alu: Ax = Ax (S)\n"); 1191 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 1, 0, IS_A1 ($1)); 1192 } 1193 else 1194 return yyerror ("Registers must be equal"); 1195 } 1196 1197 | HALF_REG ASSIGN REG LPAREN RND RPAREN 1198 { 1199 if (IS_DREG ($3)) 1200 { 1201 notethat ("dsp32alu: dregs_half = dregs (RND)\n"); 1202 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3); 1203 } 1204 else 1205 return yyerror ("Dregs expected"); 1206 } 1207 1208 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN 1209 { 1210 if (IS_DREG ($3) && IS_DREG ($5)) 1211 { 1212 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n"); 1213 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0); 1214 } 1215 else 1216 return yyerror ("Dregs expected"); 1217 } 1218 1219 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN 1220 { 1221 if (IS_DREG ($3) && IS_DREG ($5)) 1222 { 1223 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n"); 1224 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2); 1225 } 1226 else 1227 return yyerror ("Dregs expected"); 1228 } 1229 1230 | a_assign REG_A 1231 { 1232 if (!REG_SAME ($1, $2)) 1233 { 1234 notethat ("dsp32alu: An = Am\n"); 1235 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, IS_A1 ($1), 0, 3); 1236 } 1237 else 1238 return yyerror ("Accu reg arguments must differ"); 1239 } 1240 1241 | a_assign REG 1242 { 1243 if (IS_DREG ($2)) 1244 { 1245 notethat ("dsp32alu: An = dregs\n"); 1246 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1); 1247 } 1248 else 1249 return yyerror ("Dregs expected"); 1250 } 1251 1252 | REG ASSIGN HALF_REG xpmod 1253 { 1254 if (!IS_H ($3)) 1255 { 1256 if ($1.regno == REG_A0x && IS_DREG ($3)) 1257 { 1258 notethat ("dsp32alu: A0.x = dregs_lo\n"); 1259 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1); 1260 } 1261 else if ($1.regno == REG_A1x && IS_DREG ($3)) 1262 { 1263 notethat ("dsp32alu: A1.x = dregs_lo\n"); 1264 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3); 1265 } 1266 else if (IS_DREG ($1) && IS_DREG ($3)) 1267 { 1268 notethat ("ALU2op: dregs = dregs_lo\n"); 1269 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1)); 1270 } 1271 else 1272 return yyerror ("Register mismatch"); 1273 } 1274 else 1275 return yyerror ("Low reg expected"); 1276 } 1277 1278 | HALF_REG ASSIGN expr 1279 { 1280 notethat ("LDIMMhalf: pregs_half = imm16\n"); 1281 1282 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1) 1283 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1)) 1284 return yyerror ("Wrong register for load immediate"); 1285 1286 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16)) 1287 return yyerror ("Constant out of range"); 1288 1289 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3); 1290 } 1291 1292 | a_assign expr 1293 { 1294 notethat ("dsp32alu: An = 0\n"); 1295 1296 if (imm7 ($2) != 0) 1297 return yyerror ("0 expected"); 1298 1299 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1)); 1300 } 1301 1302 | REG ASSIGN expr xpmod1 1303 { 1304 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1) 1305 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1)) 1306 return yyerror ("Wrong register for load immediate"); 1307 1308 if ($4.r0 == 0) 1309 { 1310 /* 7 bit immediate value if possible. 1311 We will check for that constant value for efficiency 1312 If it goes to reloc, it will be 16 bit. */ 1313 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1)) 1314 { 1315 notethat ("COMPI2opD: dregs = imm7 (x) \n"); 1316 $$ = COMPI2OPD (&$1, imm7 ($3), 0); 1317 } 1318 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1)) 1319 { 1320 notethat ("COMPI2opP: pregs = imm7 (x)\n"); 1321 $$ = COMPI2OPP (&$1, imm7 ($3), 0); 1322 } 1323 else 1324 { 1325 if (IS_CONST ($3) && !IS_IMM ($3, 16)) 1326 return yyerror ("Immediate value out of range"); 1327 1328 notethat ("LDIMMhalf: regs = luimm16 (x)\n"); 1329 /* reg, H, S, Z. */ 1330 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3); 1331 } 1332 } 1333 else 1334 { 1335 /* (z) There is no 7 bit zero extended instruction. 1336 If the expr is a relocation, generate it. */ 1337 1338 if (IS_CONST ($3) && !IS_UIMM ($3, 16)) 1339 return yyerror ("Immediate value out of range"); 1340 1341 notethat ("LDIMMhalf: regs = luimm16 (x)\n"); 1342 /* reg, H, S, Z. */ 1343 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3); 1344 } 1345 } 1346 1347 | HALF_REG ASSIGN REG 1348 { 1349 if (IS_H ($1)) 1350 return yyerror ("Low reg expected"); 1351 1352 if (IS_DREG ($1) && $3.regno == REG_A0x) 1353 { 1354 notethat ("dsp32alu: dregs_lo = A0.x\n"); 1355 $$ = DSP32ALU (10, 0, 0, &$1, ®7, ®7, 0, 0, 0); 1356 } 1357 else if (IS_DREG ($1) && $3.regno == REG_A1x) 1358 { 1359 notethat ("dsp32alu: dregs_lo = A1.x\n"); 1360 $$ = DSP32ALU (10, 0, 0, &$1, ®7, ®7, 0, 0, 1); 1361 } 1362 else 1363 return yyerror ("Register mismatch"); 1364 } 1365 1366 | REG ASSIGN REG op_bar_op REG amod0 1367 { 1368 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)) 1369 { 1370 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n"); 1371 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0); 1372 } 1373 else 1374 return yyerror ("Register mismatch"); 1375 } 1376 1377 | REG ASSIGN BYTE_DREG xpmod 1378 { 1379 if (IS_DREG ($1) && IS_DREG ($3)) 1380 { 1381 notethat ("ALU2op: dregs = dregs_byte\n"); 1382 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1)); 1383 } 1384 else 1385 return yyerror ("Register mismatch"); 1386 } 1387 1388 | a_assign ABS REG_A COMMA a_assign ABS REG_A 1389 { 1390 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5)) 1391 { 1392 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n"); 1393 $$ = DSP32ALU (16, 0, 0, 0, ®7, ®7, 0, 0, 3); 1394 } 1395 else 1396 return yyerror ("Register mismatch"); 1397 } 1398 1399 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A 1400 { 1401 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5)) 1402 { 1403 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n"); 1404 $$ = DSP32ALU (14, 0, 0, 0, ®7, ®7, 0, 0, 3); 1405 } 1406 else 1407 return yyerror ("Register mismatch"); 1408 } 1409 1410 | a_minusassign REG_A w32_or_nothing 1411 { 1412 if (!IS_A1 ($1) && IS_A1 ($2)) 1413 { 1414 notethat ("dsp32alu: A0 -= A1\n"); 1415 $$ = DSP32ALU (11, 0, 0, 0, ®7, ®7, $3.r0, 0, 3); 1416 } 1417 else 1418 return yyerror ("Register mismatch"); 1419 } 1420 1421 | REG _MINUS_ASSIGN expr 1422 { 1423 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4) 1424 { 1425 notethat ("dagMODik: iregs -= 4\n"); 1426 $$ = DAGMODIK (&$1, 3); 1427 } 1428 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2) 1429 { 1430 notethat ("dagMODik: iregs -= 2\n"); 1431 $$ = DAGMODIK (&$1, 1); 1432 } 1433 else 1434 return yyerror ("Register or value mismatch"); 1435 } 1436 1437 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN 1438 { 1439 if (IS_IREG ($1) && IS_MREG ($3)) 1440 { 1441 notethat ("dagMODim: iregs += mregs (opt_brev)\n"); 1442 /* i, m, op, br. */ 1443 $$ = DAGMODIM (&$1, &$3, 0, 1); 1444 } 1445 else if (IS_PREG ($1) && IS_PREG ($3)) 1446 { 1447 notethat ("PTR2op: pregs += pregs (BREV )\n"); 1448 $$ = PTR2OP (&$1, &$3, 5); 1449 } 1450 else 1451 return yyerror ("Register mismatch"); 1452 } 1453 1454 | REG _MINUS_ASSIGN REG 1455 { 1456 if (IS_IREG ($1) && IS_MREG ($3)) 1457 { 1458 notethat ("dagMODim: iregs -= mregs\n"); 1459 $$ = DAGMODIM (&$1, &$3, 1, 0); 1460 } 1461 else if (IS_PREG ($1) && IS_PREG ($3)) 1462 { 1463 notethat ("PTR2op: pregs -= pregs\n"); 1464 $$ = PTR2OP (&$1, &$3, 0); 1465 } 1466 else 1467 return yyerror ("Register mismatch"); 1468 } 1469 1470 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing 1471 { 1472 if (!IS_A1 ($1) && IS_A1 ($3)) 1473 { 1474 notethat ("dsp32alu: A0 += A1 (W32)\n"); 1475 $$ = DSP32ALU (11, 0, 0, 0, ®7, ®7, $4.r0, 0, 2); 1476 } 1477 else 1478 return yyerror ("Register mismatch"); 1479 } 1480 1481 | REG _PLUS_ASSIGN REG 1482 { 1483 if (IS_IREG ($1) && IS_MREG ($3)) 1484 { 1485 notethat ("dagMODim: iregs += mregs\n"); 1486 $$ = DAGMODIM (&$1, &$3, 0, 0); 1487 } 1488 else 1489 return yyerror ("iregs += mregs expected"); 1490 } 1491 1492 | REG _PLUS_ASSIGN expr 1493 { 1494 if (IS_IREG ($1)) 1495 { 1496 if (EXPR_VALUE ($3) == 4) 1497 { 1498 notethat ("dagMODik: iregs += 4\n"); 1499 $$ = DAGMODIK (&$1, 2); 1500 } 1501 else if (EXPR_VALUE ($3) == 2) 1502 { 1503 notethat ("dagMODik: iregs += 2\n"); 1504 $$ = DAGMODIK (&$1, 0); 1505 } 1506 else 1507 return yyerror ("iregs += [ 2 | 4 "); 1508 } 1509 else if (IS_PREG ($1) && IS_IMM ($3, 7)) 1510 { 1511 notethat ("COMPI2opP: pregs += imm7\n"); 1512 $$ = COMPI2OPP (&$1, imm7 ($3), 1); 1513 } 1514 else if (IS_DREG ($1) && IS_IMM ($3, 7)) 1515 { 1516 notethat ("COMPI2opD: dregs += imm7\n"); 1517 $$ = COMPI2OPD (&$1, imm7 ($3), 1); 1518 } 1519 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3)) 1520 return yyerror ("Immediate value out of range"); 1521 else 1522 return yyerror ("Register mismatch"); 1523 } 1524 1525 | REG _STAR_ASSIGN REG 1526 { 1527 if (IS_DREG ($1) && IS_DREG ($3)) 1528 { 1529 notethat ("ALU2op: dregs *= dregs\n"); 1530 $$ = ALU2OP (&$1, &$3, 3); 1531 } 1532 else 1533 return yyerror ("Register mismatch"); 1534 } 1535 1536 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir 1537 { 1538 if (!valid_dreg_pair (&$3, $5)) 1539 return yyerror ("Bad dreg pair"); 1540 else if (!valid_dreg_pair (&$7, $9)) 1541 return yyerror ("Bad dreg pair"); 1542 else 1543 { 1544 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n"); 1545 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0); 1546 } 1547 } 1548 1549 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN 1550 { 1551 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7)) 1552 { 1553 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n"); 1554 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 1, 0, 2); 1555 } 1556 else 1557 return yyerror ("Register mismatch"); 1558 } 1559 1560 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr 1561 { 1562 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) 1563 && REG_SAME ($1, $4)) 1564 { 1565 if (EXPR_VALUE ($9) == 1) 1566 { 1567 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n"); 1568 $$ = ALU2OP (&$1, &$6, 4); 1569 } 1570 else if (EXPR_VALUE ($9) == 2) 1571 { 1572 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n"); 1573 $$ = ALU2OP (&$1, &$6, 5); 1574 } 1575 else 1576 return yyerror ("Bad shift value"); 1577 } 1578 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6) 1579 && REG_SAME ($1, $4)) 1580 { 1581 if (EXPR_VALUE ($9) == 1) 1582 { 1583 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n"); 1584 $$ = PTR2OP (&$1, &$6, 6); 1585 } 1586 else if (EXPR_VALUE ($9) == 2) 1587 { 1588 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n"); 1589 $$ = PTR2OP (&$1, &$6, 7); 1590 } 1591 else 1592 return yyerror ("Bad shift value"); 1593 } 1594 else 1595 return yyerror ("Register mismatch"); 1596 } 1597 1598 /* COMP3 CCFLAG. */ 1599 | REG ASSIGN REG BAR REG 1600 { 1601 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)) 1602 { 1603 notethat ("COMP3op: dregs = dregs | dregs\n"); 1604 $$ = COMP3OP (&$1, &$3, &$5, 3); 1605 } 1606 else 1607 return yyerror ("Dregs expected"); 1608 } 1609 | REG ASSIGN REG CARET REG 1610 { 1611 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)) 1612 { 1613 notethat ("COMP3op: dregs = dregs ^ dregs\n"); 1614 $$ = COMP3OP (&$1, &$3, &$5, 4); 1615 } 1616 else 1617 return yyerror ("Dregs expected"); 1618 } 1619 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN 1620 { 1621 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6)) 1622 { 1623 if (EXPR_VALUE ($8) == 1) 1624 { 1625 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n"); 1626 $$ = COMP3OP (&$1, &$3, &$6, 6); 1627 } 1628 else if (EXPR_VALUE ($8) == 2) 1629 { 1630 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n"); 1631 $$ = COMP3OP (&$1, &$3, &$6, 7); 1632 } 1633 else 1634 return yyerror ("Bad shift value"); 1635 } 1636 else 1637 return yyerror ("Dregs expected"); 1638 } 1639 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A 1640 { 1641 if ($3.regno == REG_A0 && $5.regno == REG_A1) 1642 { 1643 notethat ("CCflag: CC = A0 == A1\n"); 1644 $$ = CCFLAG (0, 0, 5, 0, 0); 1645 } 1646 else 1647 return yyerror ("AREGs are in bad order or same"); 1648 } 1649 | CCREG ASSIGN REG_A LESS_THAN REG_A 1650 { 1651 if ($3.regno == REG_A0 && $5.regno == REG_A1) 1652 { 1653 notethat ("CCflag: CC = A0 < A1\n"); 1654 $$ = CCFLAG (0, 0, 6, 0, 0); 1655 } 1656 else 1657 return yyerror ("AREGs are in bad order or same"); 1658 } 1659 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing 1660 { 1661 if ((IS_DREG ($3) && IS_DREG ($5)) 1662 || (IS_PREG ($3) && IS_PREG ($5))) 1663 { 1664 notethat ("CCflag: CC = dpregs < dpregs\n"); 1665 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0); 1666 } 1667 else 1668 return yyerror ("Bad register in comparison"); 1669 } 1670 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing 1671 { 1672 if (!IS_DREG ($3) && !IS_PREG ($3)) 1673 return yyerror ("Bad register in comparison"); 1674 1675 if (($6.r0 == 1 && IS_IMM ($5, 3)) 1676 || ($6.r0 == 3 && IS_UIMM ($5, 3))) 1677 { 1678 notethat ("CCflag: CC = dpregs < (u)imm3\n"); 1679 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0); 1680 } 1681 else 1682 return yyerror ("Bad constant value"); 1683 } 1684 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG 1685 { 1686 if ((IS_DREG ($3) && IS_DREG ($5)) 1687 || (IS_PREG ($3) && IS_PREG ($5))) 1688 { 1689 notethat ("CCflag: CC = dpregs == dpregs\n"); 1690 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0); 1691 } 1692 else 1693 return yyerror ("Bad register in comparison"); 1694 } 1695 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr 1696 { 1697 if (!IS_DREG ($3) && !IS_PREG ($3)) 1698 return yyerror ("Bad register in comparison"); 1699 1700 if (IS_IMM ($5, 3)) 1701 { 1702 notethat ("CCflag: CC = dpregs == imm3\n"); 1703 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0); 1704 } 1705 else 1706 return yyerror ("Bad constant range"); 1707 } 1708 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A 1709 { 1710 if ($3.regno == REG_A0 && $5.regno == REG_A1) 1711 { 1712 notethat ("CCflag: CC = A0 <= A1\n"); 1713 $$ = CCFLAG (0, 0, 7, 0, 0); 1714 } 1715 else 1716 return yyerror ("AREGs are in bad order or same"); 1717 } 1718 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing 1719 { 1720 if ((IS_DREG ($3) && IS_DREG ($5)) 1721 || (IS_PREG ($3) && IS_PREG ($5))) 1722 { 1723 notethat ("CCflag: CC = dpregs <= dpregs (..)\n"); 1724 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 1725 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0); 1726 } 1727 else 1728 return yyerror ("Bad register in comparison"); 1729 } 1730 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing 1731 { 1732 if (!IS_DREG ($3) && !IS_PREG ($3)) 1733 return yyerror ("Bad register in comparison"); 1734 1735 if (($6.r0 == 1 && IS_IMM ($5, 3)) 1736 || ($6.r0 == 3 && IS_UIMM ($5, 3))) 1737 { 1738 notethat ("CCflag: CC = dpregs <= (u)imm3\n"); 1739 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0); 1740 } 1741 else 1742 return yyerror ("Bad constant value"); 1743 } 1744 1745 | REG ASSIGN REG AMPERSAND REG 1746 { 1747 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)) 1748 { 1749 notethat ("COMP3op: dregs = dregs & dregs\n"); 1750 $$ = COMP3OP (&$1, &$3, &$5, 2); 1751 } 1752 else 1753 return yyerror ("Dregs expected"); 1754 } 1755 1756 | ccstat 1757 { 1758 notethat ("CC2stat operation\n"); 1759 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0); 1760 } 1761 1762 | REG ASSIGN REG 1763 { 1764 if ((IS_GENREG ($1) && IS_GENREG ($3)) 1765 || (IS_GENREG ($1) && IS_DAGREG ($3)) 1766 || (IS_DAGREG ($1) && IS_GENREG ($3)) 1767 || (IS_DAGREG ($1) && IS_DAGREG ($3)) 1768 || (IS_GENREG ($1) && $3.regno == REG_USP) 1769 || ($1.regno == REG_USP && IS_GENREG ($3)) 1770 || ($1.regno == REG_USP && $3.regno == REG_USP) 1771 || (IS_DREG ($1) && IS_SYSREG ($3)) 1772 || (IS_PREG ($1) && IS_SYSREG ($3)) 1773 || (IS_SYSREG ($1) && IS_GENREG ($3)) 1774 || (IS_ALLREG ($1) && IS_EMUDAT ($3)) 1775 || (IS_EMUDAT ($1) && IS_ALLREG ($3)) 1776 || (IS_SYSREG ($1) && $3.regno == REG_USP)) 1777 { 1778 $$ = bfin_gen_regmv (&$3, &$1); 1779 } 1780 else 1781 return yyerror ("Unsupported register move"); 1782 } 1783 1784 | CCREG ASSIGN REG 1785 { 1786 if (IS_DREG ($3)) 1787 { 1788 notethat ("CC2dreg: CC = dregs\n"); 1789 $$ = bfin_gen_cc2dreg (1, &$3); 1790 } 1791 else 1792 return yyerror ("Only 'CC = Dreg' supported"); 1793 } 1794 1795 | REG ASSIGN CCREG 1796 { 1797 if (IS_DREG ($1)) 1798 { 1799 notethat ("CC2dreg: dregs = CC\n"); 1800 $$ = bfin_gen_cc2dreg (0, &$1); 1801 } 1802 else 1803 return yyerror ("Only 'Dreg = CC' supported"); 1804 } 1805 1806 | CCREG _ASSIGN_BANG CCREG 1807 { 1808 notethat ("CC2dreg: CC =! CC\n"); 1809 $$ = bfin_gen_cc2dreg (3, 0); 1810 } 1811 1812 /* DSPMULT. */ 1813 1814 | HALF_REG ASSIGN multiply_halfregs opt_mode 1815 { 1816 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n"); 1817 1818 if (!IS_H ($1) && $4.MM) 1819 return yyerror ("(M) not allowed with MAC0"); 1820 1821 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS 1822 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU 1823 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH) 1824 return yyerror ("bad option."); 1825 1826 if (IS_H ($1)) 1827 { 1828 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0, 1829 IS_H ($3.s0), IS_H ($3.s1), 0, 0, 1830 &$1, 0, &$3.s0, &$3.s1, 0); 1831 } 1832 else 1833 { 1834 $$ = DSP32MULT (0, 0, $4.mod, 0, 0, 1835 0, 0, IS_H ($3.s0), IS_H ($3.s1), 1836 &$1, 0, &$3.s0, &$3.s1, 1); 1837 } 1838 } 1839 1840 | REG ASSIGN multiply_halfregs opt_mode 1841 { 1842 /* Odd registers can use (M). */ 1843 if (!IS_DREG ($1)) 1844 return yyerror ("Dreg expected"); 1845 1846 if (IS_EVEN ($1) && $4.MM) 1847 return yyerror ("(M) not allowed with MAC0"); 1848 1849 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS 1850 && $4.mod != M_S2RND && $4.mod != M_ISS2) 1851 return yyerror ("bad option"); 1852 1853 if (!IS_EVEN ($1)) 1854 { 1855 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n"); 1856 1857 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1, 1858 IS_H ($3.s0), IS_H ($3.s1), 0, 0, 1859 &$1, 0, &$3.s0, &$3.s1, 0); 1860 } 1861 else 1862 { 1863 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n"); 1864 $$ = DSP32MULT (0, 0, $4.mod, 0, 1, 1865 0, 0, IS_H ($3.s0), IS_H ($3.s1), 1866 &$1, 0, &$3.s0, &$3.s1, 1); 1867 } 1868 } 1869 1870 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA 1871 HALF_REG ASSIGN multiply_halfregs opt_mode 1872 { 1873 if (!IS_DREG ($1) || !IS_DREG ($6)) 1874 return yyerror ("Dregs expected"); 1875 1876 if (!IS_HCOMPL($1, $6)) 1877 return yyerror ("Dest registers mismatch"); 1878 1879 if (check_multiply_halfregs (&$3, &$8) < 0) 1880 return -1; 1881 1882 if ((!IS_H ($1) && $4.MM) 1883 || (!IS_H ($6) && $9.MM)) 1884 return yyerror ("(M) not allowed with MAC0"); 1885 1886 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, " 1887 "dregs_lo = multiply_halfregs opt_mode\n"); 1888 1889 if (IS_H ($1)) 1890 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0, 1891 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1), 1892 &$1, 0, &$3.s0, &$3.s1, 1); 1893 else 1894 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0, 1895 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1), 1896 &$1, 0, &$3.s0, &$3.s1, 1); 1897 } 1898 1899 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode 1900 { 1901 if (!IS_DREG ($1) || !IS_DREG ($6)) 1902 return yyerror ("Dregs expected"); 1903 1904 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1) 1905 || (IS_EVEN ($6) && $1.regno - $6.regno != 1)) 1906 return yyerror ("Dest registers mismatch"); 1907 1908 if (check_multiply_halfregs (&$3, &$8) < 0) 1909 return -1; 1910 1911 if ((IS_EVEN ($1) && $4.MM) 1912 || (IS_EVEN ($6) && $9.MM)) 1913 return yyerror ("(M) not allowed with MAC0"); 1914 1915 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, " 1916 "dregs = multiply_halfregs opt_mode\n"); 1917 1918 if (IS_EVEN ($1)) 1919 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1, 1920 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1), 1921 &$1, 0, &$3.s0, &$3.s1, 1); 1922 else 1923 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1, 1924 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1), 1925 &$1, 0, &$3.s0, &$3.s1, 1); 1926 } 1927 1928 1929 /* SHIFTs. */ 1931 | a_assign ASHIFT REG_A BY HALF_REG 1932 { 1933 if (!REG_SAME ($1, $3)) 1934 return yyerror ("Aregs must be same"); 1935 1936 if (IS_DREG ($5) && !IS_H ($5)) 1937 { 1938 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n"); 1939 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1)); 1940 } 1941 else 1942 return yyerror ("Dregs expected"); 1943 } 1944 1945 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod 1946 { 1947 if (IS_DREG ($6) && !IS_H ($6)) 1948 { 1949 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n"); 1950 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4)); 1951 } 1952 else 1953 return yyerror ("Dregs expected"); 1954 } 1955 1956 | a_assign REG_A LESS_LESS expr 1957 { 1958 if (!REG_SAME ($1, $2)) 1959 return yyerror ("Aregs must be same"); 1960 1961 if (IS_UIMM ($4, 5)) 1962 { 1963 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n"); 1964 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1)); 1965 } 1966 else 1967 return yyerror ("Bad shift value"); 1968 } 1969 1970 | REG ASSIGN REG LESS_LESS expr vsmod 1971 { 1972 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5)) 1973 { 1974 if ($6.r0) 1975 { 1976 /* Vector? */ 1977 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n"); 1978 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0); 1979 } 1980 else 1981 { 1982 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n"); 1983 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0); 1984 } 1985 } 1986 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3)) 1987 { 1988 if (EXPR_VALUE ($5) == 2) 1989 { 1990 notethat ("PTR2op: pregs = pregs << 2\n"); 1991 $$ = PTR2OP (&$1, &$3, 1); 1992 } 1993 else if (EXPR_VALUE ($5) == 1) 1994 { 1995 notethat ("COMP3op: pregs = pregs << 1\n"); 1996 $$ = COMP3OP (&$1, &$3, &$3, 5); 1997 } 1998 else 1999 return yyerror ("Bad shift value"); 2000 } 2001 else 2002 return yyerror ("Bad shift value or register"); 2003 } 2004 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod 2005 { 2006 if (IS_UIMM ($5, 4)) 2007 { 2008 if ($6.s0) 2009 { 2010 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n"); 2011 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3)); 2012 } 2013 else 2014 { 2015 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); 2016 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3)); 2017 } 2018 } 2019 else 2020 return yyerror ("Bad shift value"); 2021 } 2022 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod 2023 { 2024 int op; 2025 2026 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6)) 2027 { 2028 if ($7.r0) 2029 { 2030 op = 1; 2031 notethat ("dsp32shift: dregs = ASHIFT dregs BY " 2032 "dregs_lo (V, .)\n"); 2033 } 2034 else 2035 { 2036 2037 op = 2; 2038 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n"); 2039 } 2040 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0); 2041 } 2042 else 2043 return yyerror ("Dregs expected"); 2044 } 2045 2046 /* EXPADJ. */ 2047 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod 2048 { 2049 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7)) 2050 { 2051 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n"); 2052 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0); 2053 } 2054 else 2055 return yyerror ("Bad shift value or register"); 2056 } 2057 2058 2059 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN 2060 { 2061 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7)) 2062 { 2063 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n"); 2064 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0); 2065 } 2066 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7)) 2067 { 2068 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n"); 2069 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0); 2070 } 2071 else 2072 return yyerror ("Bad shift value or register"); 2073 } 2074 2075 /* DEPOSIT. */ 2076 2077 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN 2078 { 2079 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7)) 2080 { 2081 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n"); 2082 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0); 2083 } 2084 else 2085 return yyerror ("Register mismatch"); 2086 } 2087 2088 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN 2089 { 2090 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7)) 2091 { 2092 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n"); 2093 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0); 2094 } 2095 else 2096 return yyerror ("Register mismatch"); 2097 } 2098 2099 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod 2100 { 2101 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7)) 2102 { 2103 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n"); 2104 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0); 2105 } 2106 else 2107 return yyerror ("Register mismatch"); 2108 } 2109 2110 | a_assign REG_A _GREATER_GREATER_GREATER expr 2111 { 2112 if (!REG_SAME ($1, $2)) 2113 return yyerror ("Aregs must be same"); 2114 2115 if (IS_UIMM ($4, 5)) 2116 { 2117 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n"); 2118 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1)); 2119 } 2120 else 2121 return yyerror ("Shift value range error"); 2122 } 2123 | a_assign LSHIFT REG_A BY HALF_REG 2124 { 2125 if (REG_SAME ($1, $3) && IS_DREG_L ($5)) 2126 { 2127 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n"); 2128 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1)); 2129 } 2130 else 2131 return yyerror ("Register mismatch"); 2132 } 2133 2134 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG 2135 { 2136 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6)) 2137 { 2138 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n"); 2139 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4)); 2140 } 2141 else 2142 return yyerror ("Register mismatch"); 2143 } 2144 2145 | REG ASSIGN LSHIFT REG BY HALF_REG vmod 2146 { 2147 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6)) 2148 { 2149 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n"); 2150 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0); 2151 } 2152 else 2153 return yyerror ("Register mismatch"); 2154 } 2155 2156 | REG ASSIGN SHIFT REG BY HALF_REG 2157 { 2158 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6)) 2159 { 2160 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n"); 2161 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0); 2162 } 2163 else 2164 return yyerror ("Register mismatch"); 2165 } 2166 2167 | a_assign REG_A GREATER_GREATER expr 2168 { 2169 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0) 2170 { 2171 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n"); 2172 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1)); 2173 } 2174 else 2175 return yyerror ("Accu register expected"); 2176 } 2177 2178 | REG ASSIGN REG GREATER_GREATER expr vmod 2179 { 2180 if ($6.r0 == 1) 2181 { 2182 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5)) 2183 { 2184 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n"); 2185 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0); 2186 } 2187 else 2188 return yyerror ("Register mismatch"); 2189 } 2190 else 2191 { 2192 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5)) 2193 { 2194 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n"); 2195 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0); 2196 } 2197 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2) 2198 { 2199 notethat ("PTR2op: pregs = pregs >> 2\n"); 2200 $$ = PTR2OP (&$1, &$3, 3); 2201 } 2202 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1) 2203 { 2204 notethat ("PTR2op: pregs = pregs >> 1\n"); 2205 $$ = PTR2OP (&$1, &$3, 4); 2206 } 2207 else 2208 return yyerror ("Register mismatch"); 2209 } 2210 } 2211 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr 2212 { 2213 if (IS_UIMM ($5, 5)) 2214 { 2215 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n"); 2216 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3)); 2217 } 2218 else 2219 return yyerror ("Register mismatch"); 2220 } 2221 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod 2222 { 2223 if (IS_UIMM ($5, 5)) 2224 { 2225 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n"); 2226 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2227 $6.s0, HL2 ($1, $3)); 2228 } 2229 else 2230 return yyerror ("Register or modifier mismatch"); 2231 } 2232 2233 2234 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod 2235 { 2236 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5)) 2237 { 2238 if ($6.r0) 2239 { 2240 /* Vector? */ 2241 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n"); 2242 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0); 2243 } 2244 else 2245 { 2246 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n"); 2247 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0); 2248 } 2249 } 2250 else 2251 return yyerror ("Register mismatch"); 2252 } 2253 2254 | HALF_REG ASSIGN ONES REG 2255 { 2256 if (IS_DREG_L ($1) && IS_DREG ($4)) 2257 { 2258 notethat ("dsp32shift: dregs_lo = ONES dregs\n"); 2259 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0); 2260 } 2261 else 2262 return yyerror ("Register mismatch"); 2263 } 2264 2265 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN 2266 { 2267 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7)) 2268 { 2269 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n"); 2270 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0); 2271 } 2272 else 2273 return yyerror ("Register mismatch"); 2274 } 2275 2276 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN 2277 { 2278 if (IS_DREG ($1) 2279 && $7.regno == REG_A0 2280 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7)) 2281 { 2282 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n"); 2283 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0); 2284 } 2285 else 2286 return yyerror ("Register mismatch"); 2287 } 2288 2289 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN 2290 { 2291 if (IS_DREG ($1) 2292 && $7.regno == REG_A0 2293 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7)) 2294 { 2295 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n"); 2296 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0); 2297 } 2298 else 2299 return yyerror ("Register mismatch"); 2300 } 2301 2302 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN 2303 { 2304 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9)) 2305 { 2306 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n"); 2307 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0); 2308 } 2309 else 2310 return yyerror ("Register mismatch"); 2311 } 2312 2313 | a_assign ROT REG_A BY HALF_REG 2314 { 2315 if (REG_SAME ($1, $3) && IS_DREG_L ($5)) 2316 { 2317 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n"); 2318 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1)); 2319 } 2320 else 2321 return yyerror ("Register mismatch"); 2322 } 2323 2324 | REG ASSIGN ROT REG BY HALF_REG 2325 { 2326 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6)) 2327 { 2328 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n"); 2329 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0); 2330 } 2331 else 2332 return yyerror ("Register mismatch"); 2333 } 2334 2335 | a_assign ROT REG_A BY expr 2336 { 2337 if (IS_IMM ($5, 6)) 2338 { 2339 notethat ("dsp32shiftimm: An = ROT An BY imm6\n"); 2340 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1)); 2341 } 2342 else 2343 return yyerror ("Register mismatch"); 2344 } 2345 2346 | REG ASSIGN ROT REG BY expr 2347 { 2348 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6)) 2349 { 2350 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1)); 2351 } 2352 else 2353 return yyerror ("Register mismatch"); 2354 } 2355 2356 | HALF_REG ASSIGN SIGNBITS REG_A 2357 { 2358 if (IS_DREG_L ($1)) 2359 { 2360 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n"); 2361 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0); 2362 } 2363 else 2364 return yyerror ("Register mismatch"); 2365 } 2366 2367 | HALF_REG ASSIGN SIGNBITS REG 2368 { 2369 if (IS_DREG_L ($1) && IS_DREG ($4)) 2370 { 2371 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n"); 2372 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0); 2373 } 2374 else 2375 return yyerror ("Register mismatch"); 2376 } 2377 2378 | HALF_REG ASSIGN SIGNBITS HALF_REG 2379 { 2380 if (IS_DREG_L ($1)) 2381 { 2382 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n"); 2383 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0); 2384 } 2385 else 2386 return yyerror ("Register mismatch"); 2387 } 2388 2389 /* The ASR bit is just inverted here. */ 2390 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl 2391 { 2392 if (IS_DREG_L ($1) && IS_DREG ($5)) 2393 { 2394 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n"); 2395 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0); 2396 } 2397 else 2398 return yyerror ("Register mismatch"); 2399 } 2400 2401 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl 2402 { 2403 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7)) 2404 { 2405 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n"); 2406 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0); 2407 } 2408 else 2409 return yyerror ("Register mismatch"); 2410 } 2411 2412 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl 2413 { 2414 if (REG_SAME ($3, $5)) 2415 return yyerror ("Illegal source register combination"); 2416 2417 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7)) 2418 { 2419 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n"); 2420 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0); 2421 } 2422 else 2423 return yyerror ("Register mismatch"); 2424 } 2425 2426 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN 2427 { 2428 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6)) 2429 { 2430 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n"); 2431 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0); 2432 } 2433 else 2434 return yyerror ("Dregs expected"); 2435 } 2436 2437 2438 /* LOGI2op: BITCLR (dregs, uimm5). */ 2439 | BITCLR LPAREN REG COMMA expr RPAREN 2440 { 2441 if (IS_DREG ($3) && IS_UIMM ($5, 5)) 2442 { 2443 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n"); 2444 $$ = LOGI2OP ($3, uimm5 ($5), 4); 2445 } 2446 else 2447 return yyerror ("Register mismatch"); 2448 } 2449 2450 /* LOGI2op: BITSET (dregs, uimm5). */ 2451 | BITSET LPAREN REG COMMA expr RPAREN 2452 { 2453 if (IS_DREG ($3) && IS_UIMM ($5, 5)) 2454 { 2455 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n"); 2456 $$ = LOGI2OP ($3, uimm5 ($5), 2); 2457 } 2458 else 2459 return yyerror ("Register mismatch"); 2460 } 2461 2462 /* LOGI2op: BITTGL (dregs, uimm5). */ 2463 | BITTGL LPAREN REG COMMA expr RPAREN 2464 { 2465 if (IS_DREG ($3) && IS_UIMM ($5, 5)) 2466 { 2467 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n"); 2468 $$ = LOGI2OP ($3, uimm5 ($5), 3); 2469 } 2470 else 2471 return yyerror ("Register mismatch"); 2472 } 2473 2474 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN 2475 { 2476 if (IS_DREG ($5) && IS_UIMM ($7, 5)) 2477 { 2478 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n"); 2479 $$ = LOGI2OP ($5, uimm5 ($7), 0); 2480 } 2481 else 2482 return yyerror ("Register mismatch or value error"); 2483 } 2484 2485 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN 2486 { 2487 if (IS_DREG ($5) && IS_UIMM ($7, 5)) 2488 { 2489 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n"); 2490 $$ = LOGI2OP ($5, uimm5 ($7), 1); 2491 } 2492 else 2493 return yyerror ("Register mismatch or value error"); 2494 } 2495 2496 | IF BANG CCREG REG ASSIGN REG 2497 { 2498 if ((IS_DREG ($4) || IS_PREG ($4)) 2499 && (IS_DREG ($6) || IS_PREG ($6))) 2500 { 2501 notethat ("ccMV: IF ! CC gregs = gregs\n"); 2502 $$ = CCMV (&$6, &$4, 0); 2503 } 2504 else 2505 return yyerror ("Register mismatch"); 2506 } 2507 2508 | IF CCREG REG ASSIGN REG 2509 { 2510 if ((IS_DREG ($5) || IS_PREG ($5)) 2511 && (IS_DREG ($3) || IS_PREG ($3))) 2512 { 2513 notethat ("ccMV: IF CC gregs = gregs\n"); 2514 $$ = CCMV (&$5, &$3, 1); 2515 } 2516 else 2517 return yyerror ("Register mismatch"); 2518 } 2519 2520 | IF BANG CCREG JUMP expr 2521 { 2522 if (IS_PCREL10 ($5)) 2523 { 2524 notethat ("BRCC: IF !CC JUMP pcrel11m2\n"); 2525 $$ = BRCC (0, 0, $5); 2526 } 2527 else 2528 return yyerror ("Bad jump offset"); 2529 } 2530 2531 | IF BANG CCREG JUMP expr LPAREN BP RPAREN 2532 { 2533 if (IS_PCREL10 ($5)) 2534 { 2535 notethat ("BRCC: IF !CC JUMP pcrel11m2\n"); 2536 $$ = BRCC (0, 1, $5); 2537 } 2538 else 2539 return yyerror ("Bad jump offset"); 2540 } 2541 2542 | IF CCREG JUMP expr 2543 { 2544 if (IS_PCREL10 ($4)) 2545 { 2546 notethat ("BRCC: IF CC JUMP pcrel11m2\n"); 2547 $$ = BRCC (1, 0, $4); 2548 } 2549 else 2550 return yyerror ("Bad jump offset"); 2551 } 2552 2553 | IF CCREG JUMP expr LPAREN BP RPAREN 2554 { 2555 if (IS_PCREL10 ($4)) 2556 { 2557 notethat ("BRCC: IF !CC JUMP pcrel11m2\n"); 2558 $$ = BRCC (1, 1, $4); 2559 } 2560 else 2561 return yyerror ("Bad jump offset"); 2562 } 2563 | NOP 2564 { 2565 notethat ("ProgCtrl: NOP\n"); 2566 $$ = PROGCTRL (0, 0); 2567 } 2568 2569 | RTS 2570 { 2571 notethat ("ProgCtrl: RTS\n"); 2572 $$ = PROGCTRL (1, 0); 2573 } 2574 2575 | RTI 2576 { 2577 notethat ("ProgCtrl: RTI\n"); 2578 $$ = PROGCTRL (1, 1); 2579 } 2580 2581 | RTX 2582 { 2583 notethat ("ProgCtrl: RTX\n"); 2584 $$ = PROGCTRL (1, 2); 2585 } 2586 2587 | RTN 2588 { 2589 notethat ("ProgCtrl: RTN\n"); 2590 $$ = PROGCTRL (1, 3); 2591 } 2592 2593 | RTE 2594 { 2595 notethat ("ProgCtrl: RTE\n"); 2596 $$ = PROGCTRL (1, 4); 2597 } 2598 2599 | IDLE 2600 { 2601 notethat ("ProgCtrl: IDLE\n"); 2602 $$ = PROGCTRL (2, 0); 2603 } 2604 2605 | CSYNC 2606 { 2607 notethat ("ProgCtrl: CSYNC\n"); 2608 $$ = PROGCTRL (2, 3); 2609 } 2610 2611 | SSYNC 2612 { 2613 notethat ("ProgCtrl: SSYNC\n"); 2614 $$ = PROGCTRL (2, 4); 2615 } 2616 2617 | EMUEXCPT 2618 { 2619 notethat ("ProgCtrl: EMUEXCPT\n"); 2620 $$ = PROGCTRL (2, 5); 2621 } 2622 2623 | CLI REG 2624 { 2625 if (IS_DREG ($2)) 2626 { 2627 notethat ("ProgCtrl: CLI dregs\n"); 2628 $$ = PROGCTRL (3, $2.regno & CODE_MASK); 2629 } 2630 else 2631 return yyerror ("Dreg expected for CLI"); 2632 } 2633 2634 | STI REG 2635 { 2636 if (IS_DREG ($2)) 2637 { 2638 notethat ("ProgCtrl: STI dregs\n"); 2639 $$ = PROGCTRL (4, $2.regno & CODE_MASK); 2640 } 2641 else 2642 return yyerror ("Dreg expected for STI"); 2643 } 2644 2645 | JUMP LPAREN REG RPAREN 2646 { 2647 if (IS_PREG ($3)) 2648 { 2649 notethat ("ProgCtrl: JUMP (pregs )\n"); 2650 $$ = PROGCTRL (5, $3.regno & CODE_MASK); 2651 } 2652 else 2653 return yyerror ("Bad register for indirect jump"); 2654 } 2655 2656 | CALL LPAREN REG RPAREN 2657 { 2658 if (IS_PREG ($3)) 2659 { 2660 notethat ("ProgCtrl: CALL (pregs )\n"); 2661 $$ = PROGCTRL (6, $3.regno & CODE_MASK); 2662 } 2663 else 2664 return yyerror ("Bad register for indirect call"); 2665 } 2666 2667 | CALL LPAREN PC PLUS REG RPAREN 2668 { 2669 if (IS_PREG ($5)) 2670 { 2671 notethat ("ProgCtrl: CALL (PC + pregs )\n"); 2672 $$ = PROGCTRL (7, $5.regno & CODE_MASK); 2673 } 2674 else 2675 return yyerror ("Bad register for indirect call"); 2676 } 2677 2678 | JUMP LPAREN PC PLUS REG RPAREN 2679 { 2680 if (IS_PREG ($5)) 2681 { 2682 notethat ("ProgCtrl: JUMP (PC + pregs )\n"); 2683 $$ = PROGCTRL (8, $5.regno & CODE_MASK); 2684 } 2685 else 2686 return yyerror ("Bad register for indirect jump"); 2687 } 2688 2689 | RAISE expr 2690 { 2691 if (IS_UIMM ($2, 4)) 2692 { 2693 notethat ("ProgCtrl: RAISE uimm4\n"); 2694 $$ = PROGCTRL (9, uimm4 ($2)); 2695 } 2696 else 2697 return yyerror ("Bad value for RAISE"); 2698 } 2699 2700 | EXCPT expr 2701 { 2702 notethat ("ProgCtrl: EMUEXCPT\n"); 2703 $$ = PROGCTRL (10, uimm4 ($2)); 2704 } 2705 2706 | TESTSET LPAREN REG RPAREN 2707 { 2708 if (IS_PREG ($3)) 2709 { 2710 if ($3.regno == REG_SP || $3.regno == REG_FP) 2711 return yyerror ("Bad register for TESTSET"); 2712 2713 notethat ("ProgCtrl: TESTSET (pregs )\n"); 2714 $$ = PROGCTRL (11, $3.regno & CODE_MASK); 2715 } 2716 else 2717 return yyerror ("Preg expected"); 2718 } 2719 2720 | JUMP expr 2721 { 2722 if (IS_PCREL12 ($2)) 2723 { 2724 notethat ("UJUMP: JUMP pcrel12\n"); 2725 $$ = UJUMP ($2); 2726 } 2727 else 2728 return yyerror ("Bad value for relative jump"); 2729 } 2730 2731 | JUMP_DOT_S expr 2732 { 2733 if (IS_PCREL12 ($2)) 2734 { 2735 notethat ("UJUMP: JUMP_DOT_S pcrel12\n"); 2736 $$ = UJUMP($2); 2737 } 2738 else 2739 return yyerror ("Bad value for relative jump"); 2740 } 2741 2742 | JUMP_DOT_L expr 2743 { 2744 if (IS_PCREL24 ($2)) 2745 { 2746 notethat ("CALLa: jump.l pcrel24\n"); 2747 $$ = CALLA ($2, 0); 2748 } 2749 else 2750 return yyerror ("Bad value for long jump"); 2751 } 2752 2753 | JUMP_DOT_L pltpc 2754 { 2755 if (IS_PCREL24 ($2)) 2756 { 2757 notethat ("CALLa: jump.l pcrel24\n"); 2758 $$ = CALLA ($2, 2); 2759 } 2760 else 2761 return yyerror ("Bad value for long jump"); 2762 } 2763 2764 | CALL expr 2765 { 2766 if (IS_PCREL24 ($2)) 2767 { 2768 notethat ("CALLa: CALL pcrel25m2\n"); 2769 $$ = CALLA ($2, 1); 2770 } 2771 else 2772 return yyerror ("Bad call address"); 2773 } 2774 | CALL pltpc 2775 { 2776 if (IS_PCREL24 ($2)) 2777 { 2778 notethat ("CALLa: CALL pcrel25m2\n"); 2779 $$ = CALLA ($2, 2); 2780 } 2781 else 2782 return yyerror ("Bad call address"); 2783 } 2784 2785 /* ALU2ops. */ 2786 /* ALU2op: DIVQ (dregs, dregs). */ 2787 | DIVQ LPAREN REG COMMA REG RPAREN 2788 { 2789 if (IS_DREG ($3) && IS_DREG ($5)) 2790 $$ = ALU2OP (&$3, &$5, 8); 2791 else 2792 return yyerror ("Bad registers for DIVQ"); 2793 } 2794 2795 | DIVS LPAREN REG COMMA REG RPAREN 2796 { 2797 if (IS_DREG ($3) && IS_DREG ($5)) 2798 $$ = ALU2OP (&$3, &$5, 9); 2799 else 2800 return yyerror ("Bad registers for DIVS"); 2801 } 2802 2803 | REG ASSIGN MINUS REG vsmod 2804 { 2805 if (IS_DREG ($1) && IS_DREG ($4)) 2806 { 2807 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0) 2808 { 2809 notethat ("ALU2op: dregs = - dregs\n"); 2810 $$ = ALU2OP (&$1, &$4, 14); 2811 } 2812 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3) 2813 { 2814 notethat ("dsp32alu: dregs = - dregs (.)\n"); 2815 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3); 2816 } 2817 else 2818 { 2819 notethat ("dsp32alu: dregs = - dregs (.)\n"); 2820 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3); 2821 } 2822 } 2823 else 2824 return yyerror ("Dregs expected"); 2825 } 2826 2827 | REG ASSIGN TILDA REG 2828 { 2829 if (IS_DREG ($1) && IS_DREG ($4)) 2830 { 2831 notethat ("ALU2op: dregs = ~dregs\n"); 2832 $$ = ALU2OP (&$1, &$4, 15); 2833 } 2834 else 2835 return yyerror ("Dregs expected"); 2836 } 2837 2838 | REG _GREATER_GREATER_ASSIGN REG 2839 { 2840 if (IS_DREG ($1) && IS_DREG ($3)) 2841 { 2842 notethat ("ALU2op: dregs >>= dregs\n"); 2843 $$ = ALU2OP (&$1, &$3, 1); 2844 } 2845 else 2846 return yyerror ("Dregs expected"); 2847 } 2848 2849 | REG _GREATER_GREATER_ASSIGN expr 2850 { 2851 if (IS_DREG ($1) && IS_UIMM ($3, 5)) 2852 { 2853 notethat ("LOGI2op: dregs >>= uimm5\n"); 2854 $$ = LOGI2OP ($1, uimm5 ($3), 6); 2855 } 2856 else 2857 return yyerror ("Dregs expected or value error"); 2858 } 2859 2860 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG 2861 { 2862 if (IS_DREG ($1) && IS_DREG ($3)) 2863 { 2864 notethat ("ALU2op: dregs >>>= dregs\n"); 2865 $$ = ALU2OP (&$1, &$3, 0); 2866 } 2867 else 2868 return yyerror ("Dregs expected"); 2869 } 2870 2871 | REG _LESS_LESS_ASSIGN REG 2872 { 2873 if (IS_DREG ($1) && IS_DREG ($3)) 2874 { 2875 notethat ("ALU2op: dregs <<= dregs\n"); 2876 $$ = ALU2OP (&$1, &$3, 2); 2877 } 2878 else 2879 return yyerror ("Dregs expected"); 2880 } 2881 2882 | REG _LESS_LESS_ASSIGN expr 2883 { 2884 if (IS_DREG ($1) && IS_UIMM ($3, 5)) 2885 { 2886 notethat ("LOGI2op: dregs <<= uimm5\n"); 2887 $$ = LOGI2OP ($1, uimm5 ($3), 7); 2888 } 2889 else 2890 return yyerror ("Dregs expected or const value error"); 2891 } 2892 2893 2894 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr 2895 { 2896 if (IS_DREG ($1) && IS_UIMM ($3, 5)) 2897 { 2898 notethat ("LOGI2op: dregs >>>= uimm5\n"); 2899 $$ = LOGI2OP ($1, uimm5 ($3), 5); 2900 } 2901 else 2902 return yyerror ("Dregs expected"); 2903 } 2904 2905 /* Cache Control. */ 2906 2907 | FLUSH LBRACK REG RBRACK 2908 { 2909 notethat ("CaCTRL: FLUSH [ pregs ]\n"); 2910 if (IS_PREG ($3)) 2911 $$ = CACTRL (&$3, 0, 2); 2912 else 2913 return yyerror ("Bad register(s) for FLUSH"); 2914 } 2915 2916 | FLUSH reg_with_postinc 2917 { 2918 if (IS_PREG ($2)) 2919 { 2920 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n"); 2921 $$ = CACTRL (&$2, 1, 2); 2922 } 2923 else 2924 return yyerror ("Bad register(s) for FLUSH"); 2925 } 2926 2927 | FLUSHINV LBRACK REG RBRACK 2928 { 2929 if (IS_PREG ($3)) 2930 { 2931 notethat ("CaCTRL: FLUSHINV [ pregs ]\n"); 2932 $$ = CACTRL (&$3, 0, 1); 2933 } 2934 else 2935 return yyerror ("Bad register(s) for FLUSH"); 2936 } 2937 2938 | FLUSHINV reg_with_postinc 2939 { 2940 if (IS_PREG ($2)) 2941 { 2942 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n"); 2943 $$ = CACTRL (&$2, 1, 1); 2944 } 2945 else 2946 return yyerror ("Bad register(s) for FLUSH"); 2947 } 2948 2949 /* CaCTRL: IFLUSH [pregs]. */ 2950 | IFLUSH LBRACK REG RBRACK 2951 { 2952 if (IS_PREG ($3)) 2953 { 2954 notethat ("CaCTRL: IFLUSH [ pregs ]\n"); 2955 $$ = CACTRL (&$3, 0, 3); 2956 } 2957 else 2958 return yyerror ("Bad register(s) for FLUSH"); 2959 } 2960 2961 | IFLUSH reg_with_postinc 2962 { 2963 if (IS_PREG ($2)) 2964 { 2965 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n"); 2966 $$ = CACTRL (&$2, 1, 3); 2967 } 2968 else 2969 return yyerror ("Bad register(s) for FLUSH"); 2970 } 2971 2972 | PREFETCH LBRACK REG RBRACK 2973 { 2974 if (IS_PREG ($3)) 2975 { 2976 notethat ("CaCTRL: PREFETCH [ pregs ]\n"); 2977 $$ = CACTRL (&$3, 0, 0); 2978 } 2979 else 2980 return yyerror ("Bad register(s) for PREFETCH"); 2981 } 2982 2983 | PREFETCH reg_with_postinc 2984 { 2985 if (IS_PREG ($2)) 2986 { 2987 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n"); 2988 $$ = CACTRL (&$2, 1, 0); 2989 } 2990 else 2991 return yyerror ("Bad register(s) for PREFETCH"); 2992 } 2993 2994 /* LOAD/STORE. */ 2995 /* LDST: B [ pregs <post_op> ] = dregs. */ 2996 2997 | B LBRACK REG post_op RBRACK ASSIGN REG 2998 { 2999 if (!IS_DREG ($7)) 3000 return yyerror ("Dreg expected for source operand"); 3001 if (!IS_PREG ($3)) 3002 return yyerror ("Preg expected in address"); 3003 3004 notethat ("LDST: B [ pregs <post_op> ] = dregs\n"); 3005 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1); 3006 } 3007 3008 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */ 3009 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG 3010 { 3011 Expr_Node *tmp = $5; 3012 3013 if (!IS_DREG ($8)) 3014 return yyerror ("Dreg expected for source operand"); 3015 if (!IS_PREG ($3)) 3016 return yyerror ("Preg expected in address"); 3017 3018 if (IS_RELOC ($5)) 3019 return yyerror ("Plain symbol used as offset"); 3020 3021 if ($4.r0) 3022 tmp = unary (Expr_Op_Type_NEG, tmp); 3023 3024 if (in_range_p (tmp, -32768, 32767, 0)) 3025 { 3026 notethat ("LDST: B [ pregs + imm16 ] = dregs\n"); 3027 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5); 3028 } 3029 else 3030 return yyerror ("Displacement out of range"); 3031 } 3032 3033 3034 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */ 3035 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG 3036 { 3037 Expr_Node *tmp = $5; 3038 3039 if (!IS_DREG ($8)) 3040 return yyerror ("Dreg expected for source operand"); 3041 if (!IS_PREG ($3)) 3042 return yyerror ("Preg expected in address"); 3043 3044 if ($4.r0) 3045 tmp = unary (Expr_Op_Type_NEG, tmp); 3046 3047 if (IS_RELOC ($5)) 3048 return yyerror ("Plain symbol used as offset"); 3049 3050 if (in_range_p (tmp, 0, 30, 1)) 3051 { 3052 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n"); 3053 $$ = LDSTII (&$3, &$8, tmp, 1, 1); 3054 } 3055 else if (in_range_p (tmp, -65536, 65535, 1)) 3056 { 3057 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n"); 3058 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp); 3059 } 3060 else 3061 return yyerror ("Displacement out of range"); 3062 } 3063 3064 /* LDST: W [ pregs <post_op> ] = dregs. */ 3065 | W LBRACK REG post_op RBRACK ASSIGN REG 3066 { 3067 if (!IS_DREG ($7)) 3068 return yyerror ("Dreg expected for source operand"); 3069 if (!IS_PREG ($3)) 3070 return yyerror ("Preg expected in address"); 3071 3072 notethat ("LDST: W [ pregs <post_op> ] = dregs\n"); 3073 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1); 3074 } 3075 3076 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG 3077 { 3078 if (!IS_DREG ($7)) 3079 return yyerror ("Dreg expected for source operand"); 3080 if ($4.x0 == 2) 3081 { 3082 if (!IS_IREG ($3) && !IS_PREG ($3)) 3083 return yyerror ("Ireg or Preg expected in address"); 3084 } 3085 else if (!IS_IREG ($3)) 3086 return yyerror ("Ireg expected in address"); 3087 3088 if (IS_IREG ($3)) 3089 { 3090 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n"); 3091 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1); 3092 } 3093 else 3094 { 3095 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n"); 3096 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1); 3097 } 3098 } 3099 3100 /* LDSTiiFP: [ FP - const ] = dpregs. */ 3101 | LBRACK REG plus_minus expr RBRACK ASSIGN REG 3102 { 3103 Expr_Node *tmp = $4; 3104 int ispreg = IS_PREG ($7); 3105 3106 if (!IS_PREG ($2)) 3107 return yyerror ("Preg expected in address"); 3108 3109 if (!IS_DREG ($7) && !ispreg) 3110 return yyerror ("Preg expected for source operand"); 3111 3112 if ($3.r0) 3113 tmp = unary (Expr_Op_Type_NEG, tmp); 3114 3115 if (IS_RELOC ($4)) 3116 return yyerror ("Plain symbol used as offset"); 3117 3118 if (in_range_p (tmp, 0, 63, 3)) 3119 { 3120 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n"); 3121 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0); 3122 } 3123 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3)) 3124 { 3125 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n"); 3126 tmp = unary (Expr_Op_Type_NEG, tmp); 3127 $$ = LDSTIIFP (tmp, &$7, 1); 3128 } 3129 else if (in_range_p (tmp, -131072, 131071, 3)) 3130 { 3131 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n"); 3132 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp); 3133 } 3134 else 3135 return yyerror ("Displacement out of range"); 3136 } 3137 3138 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod 3139 { 3140 Expr_Node *tmp = $7; 3141 if (!IS_DREG ($1)) 3142 return yyerror ("Dreg expected for destination operand"); 3143 if (!IS_PREG ($5)) 3144 return yyerror ("Preg expected in address"); 3145 3146 if ($6.r0) 3147 tmp = unary (Expr_Op_Type_NEG, tmp); 3148 3149 if (IS_RELOC ($7)) 3150 return yyerror ("Plain symbol used as offset"); 3151 3152 if (in_range_p (tmp, 0, 30, 1)) 3153 { 3154 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n"); 3155 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0); 3156 } 3157 else if (in_range_p (tmp, -65536, 65535, 1)) 3158 { 3159 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n"); 3160 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp); 3161 } 3162 else 3163 return yyerror ("Displacement out of range"); 3164 } 3165 3166 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK 3167 { 3168 if (!IS_DREG ($1)) 3169 return yyerror ("Dreg expected for source operand"); 3170 if ($6.x0 == 2) 3171 { 3172 if (!IS_IREG ($5) && !IS_PREG ($5)) 3173 return yyerror ("Ireg or Preg expected in address"); 3174 } 3175 else if (!IS_IREG ($5)) 3176 return yyerror ("Ireg expected in address"); 3177 3178 if (IS_IREG ($5)) 3179 { 3180 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n"); 3181 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0); 3182 } 3183 else 3184 { 3185 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n"); 3186 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0); 3187 } 3188 } 3189 3190 3191 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod 3192 { 3193 if (!IS_DREG ($1)) 3194 return yyerror ("Dreg expected for destination operand"); 3195 if (!IS_PREG ($5)) 3196 return yyerror ("Preg expected in address"); 3197 3198 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n"); 3199 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0); 3200 } 3201 3202 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod 3203 { 3204 if (!IS_DREG ($1)) 3205 return yyerror ("Dreg expected for destination operand"); 3206 if (!IS_PREG ($5) || !IS_PREG ($7)) 3207 return yyerror ("Preg expected in address"); 3208 3209 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n"); 3210 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0); 3211 } 3212 3213 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK 3214 { 3215 if (!IS_DREG ($1)) 3216 return yyerror ("Dreg expected for destination operand"); 3217 if (!IS_PREG ($5) || !IS_PREG ($7)) 3218 return yyerror ("Preg expected in address"); 3219 3220 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n"); 3221 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0); 3222 } 3223 3224 | LBRACK REG post_op RBRACK ASSIGN REG 3225 { 3226 if (!IS_IREG ($2) && !IS_PREG ($2)) 3227 return yyerror ("Ireg or Preg expected in address"); 3228 else if (IS_IREG ($2) && !IS_DREG ($6)) 3229 return yyerror ("Dreg expected for source operand"); 3230 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6)) 3231 return yyerror ("Dreg or Preg expected for source operand"); 3232 3233 if (IS_IREG ($2)) 3234 { 3235 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n"); 3236 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1); 3237 } 3238 else if (IS_DREG ($6)) 3239 { 3240 notethat ("LDST: [ pregs <post_op> ] = dregs\n"); 3241 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1); 3242 } 3243 else 3244 { 3245 notethat ("LDST: [ pregs <post_op> ] = pregs\n"); 3246 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1); 3247 } 3248 } 3249 3250 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG 3251 { 3252 if (!IS_DREG ($7)) 3253 return yyerror ("Dreg expected for source operand"); 3254 3255 if (IS_IREG ($2) && IS_MREG ($4)) 3256 { 3257 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n"); 3258 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1); 3259 } 3260 else if (IS_PREG ($2) && IS_PREG ($4)) 3261 { 3262 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n"); 3263 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1); 3264 } 3265 else 3266 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address"); 3267 } 3268 3269 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG 3270 { 3271 if (!IS_DREG ($8)) 3272 return yyerror ("Dreg expected for source operand"); 3273 3274 if (IS_PREG ($3) && IS_PREG ($5)) 3275 { 3276 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n"); 3277 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1); 3278 } 3279 else 3280 return yyerror ("Preg ++ Preg expected in address"); 3281 } 3282 3283 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod 3284 { 3285 Expr_Node *tmp = $7; 3286 if (!IS_DREG ($1)) 3287 return yyerror ("Dreg expected for destination operand"); 3288 if (!IS_PREG ($5)) 3289 return yyerror ("Preg expected in address"); 3290 3291 if ($6.r0) 3292 tmp = unary (Expr_Op_Type_NEG, tmp); 3293 3294 if (IS_RELOC ($7)) 3295 return yyerror ("Plain symbol used as offset"); 3296 3297 if (in_range_p (tmp, -32768, 32767, 0)) 3298 { 3299 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n", 3300 $9.r0 ? 'X' : 'Z'); 3301 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp); 3302 } 3303 else 3304 return yyerror ("Displacement out of range"); 3305 } 3306 3307 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod 3308 { 3309 if (!IS_DREG ($1)) 3310 return yyerror ("Dreg expected for destination operand"); 3311 if (!IS_PREG ($5)) 3312 return yyerror ("Preg expected in address"); 3313 3314 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n", 3315 $8.r0 ? 'X' : 'Z'); 3316 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0); 3317 } 3318 3319 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK 3320 { 3321 if (!IS_DREG ($1)) 3322 return yyerror ("Dreg expected for destination operand"); 3323 3324 if (IS_IREG ($4) && IS_MREG ($6)) 3325 { 3326 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n"); 3327 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0); 3328 } 3329 else if (IS_PREG ($4) && IS_PREG ($6)) 3330 { 3331 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n"); 3332 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0); 3333 } 3334 else 3335 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address"); 3336 } 3337 3338 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK 3339 { 3340 Expr_Node *tmp = $6; 3341 int ispreg = IS_PREG ($1); 3342 int isgot = IS_RELOC($6); 3343 3344 if (!IS_PREG ($4)) 3345 return yyerror ("Preg expected in address"); 3346 3347 if (!IS_DREG ($1) && !ispreg) 3348 return yyerror ("Dreg or Preg expected for destination operand"); 3349 3350 if (tmp->type == Expr_Node_Reloc 3351 && strcmp (tmp->value.s_value, 3352 "_current_shared_library_p5_offset_") != 0) 3353 return yyerror ("Plain symbol used as offset"); 3354 3355 if ($5.r0) 3356 tmp = unary (Expr_Op_Type_NEG, tmp); 3357 3358 if (isgot) 3359 { 3360 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n"); 3361 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp); 3362 } 3363 else if (in_range_p (tmp, 0, 63, 3)) 3364 { 3365 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n"); 3366 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0); 3367 } 3368 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3)) 3369 { 3370 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n"); 3371 tmp = unary (Expr_Op_Type_NEG, tmp); 3372 $$ = LDSTIIFP (tmp, &$1, 0); 3373 } 3374 else if (in_range_p (tmp, -131072, 131071, 3)) 3375 { 3376 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n"); 3377 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp); 3378 3379 } 3380 else 3381 return yyerror ("Displacement out of range"); 3382 } 3383 3384 | REG ASSIGN LBRACK REG post_op RBRACK 3385 { 3386 if (!IS_IREG ($4) && !IS_PREG ($4)) 3387 return yyerror ("Ireg or Preg expected in address"); 3388 else if (IS_IREG ($4) && !IS_DREG ($1)) 3389 return yyerror ("Dreg expected in destination operand"); 3390 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1) 3391 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0)) 3392 return yyerror ("Dreg or Preg expected in destination operand"); 3393 3394 if (IS_IREG ($4)) 3395 { 3396 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n"); 3397 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0); 3398 } 3399 else if (IS_DREG ($1)) 3400 { 3401 notethat ("LDST: dregs = [ pregs <post_op> ]\n"); 3402 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0); 3403 } 3404 else if (IS_PREG ($1)) 3405 { 3406 if (REG_SAME ($1, $4) && $5.x0 != 2) 3407 return yyerror ("Pregs can't be same"); 3408 3409 notethat ("LDST: pregs = [ pregs <post_op> ]\n"); 3410 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0); 3411 } 3412 else 3413 { 3414 notethat ("PushPopReg: allregs = [ SP ++ ]\n"); 3415 $$ = PUSHPOPREG (&$1, 0); 3416 } 3417 } 3418 3419 3420 /* PushPopMultiple. */ 3421 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN 3422 { 3423 if ($1.regno != REG_SP) 3424 yyerror ("Stack Pointer expected"); 3425 if ($4.regno == REG_R7 3426 && IN_RANGE ($6, 0, 7) 3427 && $8.regno == REG_P5 3428 && IN_RANGE ($10, 0, 5)) 3429 { 3430 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n"); 3431 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1); 3432 } 3433 else 3434 return yyerror ("Bad register for PushPopMultiple"); 3435 } 3436 3437 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN 3438 { 3439 if ($1.regno != REG_SP) 3440 yyerror ("Stack Pointer expected"); 3441 3442 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7)) 3443 { 3444 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n"); 3445 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1); 3446 } 3447 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6)) 3448 { 3449 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n"); 3450 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1); 3451 } 3452 else 3453 return yyerror ("Bad register for PushPopMultiple"); 3454 } 3455 3456 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc 3457 { 3458 if ($11.regno != REG_SP) 3459 yyerror ("Stack Pointer expected"); 3460 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7)) 3461 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6))) 3462 { 3463 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n"); 3464 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0); 3465 } 3466 else 3467 return yyerror ("Bad register range for PushPopMultiple"); 3468 } 3469 3470 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc 3471 { 3472 if ($7.regno != REG_SP) 3473 yyerror ("Stack Pointer expected"); 3474 3475 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7)) 3476 { 3477 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n"); 3478 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0); 3479 } 3480 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6)) 3481 { 3482 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n"); 3483 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0); 3484 } 3485 else 3486 return yyerror ("Bad register range for PushPopMultiple"); 3487 } 3488 3489 | reg_with_predec ASSIGN REG 3490 { 3491 if ($1.regno != REG_SP) 3492 yyerror ("Stack Pointer expected"); 3493 3494 if (IS_ALLREG ($3)) 3495 { 3496 notethat ("PushPopReg: [ -- SP ] = allregs\n"); 3497 $$ = PUSHPOPREG (&$3, 1); 3498 } 3499 else 3500 return yyerror ("Bad register for PushPopReg"); 3501 } 3502 3503 /* Linkage. */ 3504 3505 | LINK expr 3506 { 3507 if (IS_URANGE (16, $2, 0, 4)) 3508 $$ = LINKAGE (0, uimm16s4 ($2)); 3509 else 3510 return yyerror ("Bad constant for LINK"); 3511 } 3512 3513 | UNLINK 3514 { 3515 notethat ("linkage: UNLINK\n"); 3516 $$ = LINKAGE (1, 0); 3517 } 3518 3519 3520 /* LSETUP. */ 3521 3522 | LSETUP LPAREN expr COMMA expr RPAREN REG 3523 { 3524 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7)) 3525 { 3526 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n"); 3527 $$ = LOOPSETUP ($3, &$7, 0, $5, 0); 3528 } 3529 else 3530 return yyerror ("Bad register or values for LSETUP"); 3531 3532 } 3533 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG 3534 { 3535 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) 3536 && IS_PREG ($9) && IS_CREG ($7)) 3537 { 3538 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n"); 3539 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9); 3540 } 3541 else 3542 return yyerror ("Bad register or values for LSETUP"); 3543 } 3544 3545 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr 3546 { 3547 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) 3548 && IS_PREG ($9) && IS_CREG ($7) 3549 && EXPR_VALUE ($11) == 1) 3550 { 3551 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n"); 3552 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9); 3553 } 3554 else 3555 return yyerror ("Bad register or values for LSETUP"); 3556 } 3557 3558 /* LOOP. */ 3559 | LOOP expr REG 3560 { 3561 if (!IS_RELOC ($2)) 3562 return yyerror ("Invalid expression in loop statement"); 3563 if (!IS_CREG ($3)) 3564 return yyerror ("Invalid loop counter register"); 3565 $$ = bfin_gen_loop ($2, &$3, 0, 0); 3566 } 3567 | LOOP expr REG ASSIGN REG 3568 { 3569 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3)) 3570 { 3571 notethat ("Loop: LOOP expr counters = pregs\n"); 3572 $$ = bfin_gen_loop ($2, &$3, 1, &$5); 3573 } 3574 else 3575 return yyerror ("Bad register or values for LOOP"); 3576 } 3577 | LOOP expr REG ASSIGN REG GREATER_GREATER expr 3578 { 3579 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1) 3580 { 3581 notethat ("Loop: LOOP expr counters = pregs >> 1\n"); 3582 $$ = bfin_gen_loop ($2, &$3, 3, &$5); 3583 } 3584 else 3585 return yyerror ("Bad register or values for LOOP"); 3586 } 3587 3588 /* LOOP_BEGIN. */ 3589 | LOOP_BEGIN NUMBER 3590 { 3591 Expr_Node_Value val; 3592 val.i_value = $2; 3593 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL); 3594 bfin_loop_attempt_create_label (tmp, 1); 3595 if (!IS_RELOC (tmp)) 3596 return yyerror ("Invalid expression in LOOP_BEGIN statement"); 3597 bfin_loop_beginend (tmp, 1); 3598 $$ = 0; 3599 } 3600 | LOOP_BEGIN expr 3601 { 3602 if (!IS_RELOC ($2)) 3603 return yyerror ("Invalid expression in LOOP_BEGIN statement"); 3604 3605 bfin_loop_beginend ($2, 1); 3606 $$ = 0; 3607 } 3608 3609 /* LOOP_END. */ 3610 | LOOP_END NUMBER 3611 { 3612 Expr_Node_Value val; 3613 val.i_value = $2; 3614 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL); 3615 bfin_loop_attempt_create_label (tmp, 1); 3616 if (!IS_RELOC (tmp)) 3617 return yyerror ("Invalid expression in LOOP_END statement"); 3618 bfin_loop_beginend (tmp, 0); 3619 $$ = 0; 3620 } 3621 | LOOP_END expr 3622 { 3623 if (!IS_RELOC ($2)) 3624 return yyerror ("Invalid expression in LOOP_END statement"); 3625 3626 bfin_loop_beginend ($2, 0); 3627 $$ = 0; 3628 } 3629 3630 /* pseudoDEBUG. */ 3631 3632 | ABORT 3633 { 3634 notethat ("psedoDEBUG: ABORT\n"); 3635 $$ = bfin_gen_pseudodbg (3, 3, 0); 3636 } 3637 3638 | DBG 3639 { 3640 notethat ("pseudoDEBUG: DBG\n"); 3641 $$ = bfin_gen_pseudodbg (3, 7, 0); 3642 } 3643 | DBG REG_A 3644 { 3645 notethat ("pseudoDEBUG: DBG REG_A\n"); 3646 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0); 3647 } 3648 | DBG REG 3649 { 3650 notethat ("pseudoDEBUG: DBG allregs\n"); 3651 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4); 3652 } 3653 3654 | DBGCMPLX LPAREN REG RPAREN 3655 { 3656 if (!IS_DREG ($3)) 3657 return yyerror ("Dregs expected"); 3658 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n"); 3659 $$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4); 3660 } 3661 3662 | DBGHALT 3663 { 3664 notethat ("psedoDEBUG: DBGHALT\n"); 3665 $$ = bfin_gen_pseudodbg (3, 5, 0); 3666 } 3667 3668 | HLT 3669 { 3670 notethat ("psedoDEBUG: HLT\n"); 3671 $$ = bfin_gen_pseudodbg (3, 4, 0); 3672 } 3673 3674 | DBGA LPAREN HALF_REG COMMA expr RPAREN 3675 { 3676 notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n"); 3677 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5)); 3678 } 3679 3680 | DBGAH LPAREN REG COMMA expr RPAREN 3681 { 3682 notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n"); 3683 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5)); 3684 } 3685 3686 | DBGAL LPAREN REG COMMA expr RPAREN 3687 { 3688 notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n"); 3689 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5)); 3690 } 3691 3692 | OUTC expr 3693 { 3694 if (!IS_UIMM ($2, 8)) 3695 return yyerror ("Constant out of range"); 3696 notethat ("psedodbg_assert: OUTC uimm8\n"); 3697 $$ = bfin_gen_pseudochr (uimm8 ($2)); 3698 } 3699 3700 | OUTC REG 3701 { 3702 if (!IS_DREG ($2)) 3703 return yyerror ("Dregs expected"); 3704 notethat ("psedodbg_assert: OUTC dreg\n"); 3705 $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0); 3706 } 3707 3708 ; 3709 3710 /* AUX RULES. */ 3711 3712 /* Register rules. */ 3713 3714 REG_A: REG_A_DOUBLE_ZERO 3715 { 3716 $$ = $1; 3717 } 3718 | REG_A_DOUBLE_ONE 3719 { 3720 $$ = $1; 3721 } 3722 ; 3723 3724 3725 /* Modifiers. */ 3726 3727 opt_mode: 3728 { 3729 $$.MM = 0; 3730 $$.mod = 0; 3731 } 3732 | LPAREN M COMMA MMOD RPAREN 3733 { 3734 $$.MM = 1; 3735 $$.mod = $4; 3736 } 3737 | LPAREN MMOD COMMA M RPAREN 3738 { 3739 $$.MM = 1; 3740 $$.mod = $2; 3741 } 3742 | LPAREN MMOD RPAREN 3743 { 3744 $$.MM = 0; 3745 $$.mod = $2; 3746 } 3747 | LPAREN M RPAREN 3748 { 3749 $$.MM = 1; 3750 $$.mod = 0; 3751 } 3752 ; 3753 3754 asr_asl: LPAREN ASL RPAREN 3755 { 3756 $$.r0 = 1; 3757 } 3758 | LPAREN ASR RPAREN 3759 { 3760 $$.r0 = 0; 3761 } 3762 ; 3763 3764 sco: 3765 { 3766 $$.s0 = 0; 3767 $$.x0 = 0; 3768 } 3769 | S 3770 { 3771 $$.s0 = 1; 3772 $$.x0 = 0; 3773 } 3774 | CO 3775 { 3776 $$.s0 = 0; 3777 $$.x0 = 1; 3778 } 3779 | SCO 3780 { 3781 $$.s0 = 1; 3782 $$.x0 = 1; 3783 } 3784 ; 3785 3786 asr_asl_0: 3787 ASL 3788 { 3789 $$.r0 = 1; 3790 } 3791 | ASR 3792 { 3793 $$.r0 = 0; 3794 } 3795 ; 3796 3797 amod0: 3798 { 3799 $$.s0 = 0; 3800 $$.x0 = 0; 3801 } 3802 | LPAREN sco RPAREN 3803 { 3804 $$.s0 = $2.s0; 3805 $$.x0 = $2.x0; 3806 } 3807 ; 3808 3809 amod1: 3810 { 3811 $$.s0 = 0; 3812 $$.x0 = 0; 3813 $$.aop = 0; 3814 } 3815 | LPAREN NS RPAREN 3816 { 3817 $$.s0 = 0; 3818 $$.x0 = 0; 3819 $$.aop = 1; 3820 } 3821 | LPAREN S RPAREN 3822 { 3823 $$.s0 = 1; 3824 $$.x0 = 0; 3825 $$.aop = 1; 3826 } 3827 ; 3828 3829 amod2: 3830 { 3831 $$.r0 = 0; 3832 $$.s0 = 0; 3833 $$.x0 = 0; 3834 } 3835 | LPAREN asr_asl_0 RPAREN 3836 { 3837 $$.r0 = 2 + $2.r0; 3838 $$.s0 = 0; 3839 $$.x0 = 0; 3840 } 3841 | LPAREN sco RPAREN 3842 { 3843 $$.r0 = 0; 3844 $$.s0 = $2.s0; 3845 $$.x0 = $2.x0; 3846 } 3847 | LPAREN asr_asl_0 COMMA sco RPAREN 3848 { 3849 $$.r0 = 2 + $2.r0; 3850 $$.s0 = $4.s0; 3851 $$.x0 = $4.x0; 3852 } 3853 | LPAREN sco COMMA asr_asl_0 RPAREN 3854 { 3855 $$.r0 = 2 + $4.r0; 3856 $$.s0 = $2.s0; 3857 $$.x0 = $2.x0; 3858 } 3859 ; 3860 3861 xpmod: 3862 { 3863 $$.r0 = 0; 3864 } 3865 | LPAREN Z RPAREN 3866 { 3867 $$.r0 = 0; 3868 } 3869 | LPAREN X RPAREN 3870 { 3871 $$.r0 = 1; 3872 } 3873 ; 3874 3875 xpmod1: 3876 { 3877 $$.r0 = 0; 3878 } 3879 | LPAREN X RPAREN 3880 { 3881 $$.r0 = 0; 3882 } 3883 | LPAREN Z RPAREN 3884 { 3885 $$.r0 = 1; 3886 } 3887 ; 3888 3889 vsmod: 3890 { 3891 $$.r0 = 0; 3892 $$.s0 = 0; 3893 $$.aop = 0; 3894 } 3895 | LPAREN NS RPAREN 3896 { 3897 $$.r0 = 0; 3898 $$.s0 = 0; 3899 $$.aop = 3; 3900 } 3901 | LPAREN S RPAREN 3902 { 3903 $$.r0 = 0; 3904 $$.s0 = 1; 3905 $$.aop = 3; 3906 } 3907 | LPAREN V RPAREN 3908 { 3909 $$.r0 = 1; 3910 $$.s0 = 0; 3911 $$.aop = 3; 3912 } 3913 | LPAREN V COMMA S RPAREN 3914 { 3915 $$.r0 = 1; 3916 $$.s0 = 1; 3917 } 3918 | LPAREN S COMMA V RPAREN 3919 { 3920 $$.r0 = 1; 3921 $$.s0 = 1; 3922 } 3923 ; 3924 3925 vmod: 3926 { 3927 $$.r0 = 0; 3928 } 3929 | LPAREN V RPAREN 3930 { 3931 $$.r0 = 1; 3932 } 3933 ; 3934 3935 smod: 3936 { 3937 $$.s0 = 0; 3938 } 3939 | LPAREN S RPAREN 3940 { 3941 $$.s0 = 1; 3942 } 3943 ; 3944 3945 searchmod: 3946 GE 3947 { 3948 $$.r0 = 1; 3949 } 3950 | GT 3951 { 3952 $$.r0 = 0; 3953 } 3954 | LE 3955 { 3956 $$.r0 = 3; 3957 } 3958 | LT 3959 { 3960 $$.r0 = 2; 3961 } 3962 ; 3963 3964 aligndir: 3965 { 3966 $$.r0 = 0; 3967 } 3968 | LPAREN R RPAREN 3969 { 3970 $$.r0 = 1; 3971 } 3972 ; 3973 3974 byteop_mod: 3975 LPAREN R RPAREN 3976 { 3977 $$.r0 = 0; 3978 $$.s0 = 1; 3979 } 3980 | LPAREN MMOD RPAREN 3981 { 3982 if ($2 != M_T) 3983 return yyerror ("Bad modifier"); 3984 $$.r0 = 1; 3985 $$.s0 = 0; 3986 } 3987 | LPAREN MMOD COMMA R RPAREN 3988 { 3989 if ($2 != M_T) 3990 return yyerror ("Bad modifier"); 3991 $$.r0 = 1; 3992 $$.s0 = 1; 3993 } 3994 | LPAREN R COMMA MMOD RPAREN 3995 { 3996 if ($4 != M_T) 3997 return yyerror ("Bad modifier"); 3998 $$.r0 = 1; 3999 $$.s0 = 1; 4000 } 4001 ; 4002 4003 4004 4005 c_align: 4006 ALIGN8 4007 { 4008 $$.r0 = 0; 4009 } 4010 | ALIGN16 4011 { 4012 $$.r0 = 1; 4013 } 4014 | ALIGN24 4015 { 4016 $$.r0 = 2; 4017 } 4018 ; 4019 4020 w32_or_nothing: 4021 { 4022 $$.r0 = 0; 4023 } 4024 | LPAREN MMOD RPAREN 4025 { 4026 if ($2 == M_W32) 4027 $$.r0 = 1; 4028 else 4029 return yyerror ("Only (W32) allowed"); 4030 } 4031 ; 4032 4033 iu_or_nothing: 4034 { 4035 $$.r0 = 1; 4036 } 4037 | LPAREN MMOD RPAREN 4038 { 4039 if ($2 == M_IU) 4040 $$.r0 = 3; 4041 else 4042 return yyerror ("(IU) expected"); 4043 } 4044 ; 4045 4046 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK 4047 { 4048 $$ = $3; 4049 } 4050 ; 4051 4052 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK 4053 { 4054 $$ = $2; 4055 } 4056 ; 4057 4058 /* Operators. */ 4059 4060 min_max: 4061 MIN 4062 { 4063 $$.r0 = 1; 4064 } 4065 | MAX 4066 { 4067 $$.r0 = 0; 4068 } 4069 ; 4070 4071 op_bar_op: 4072 _PLUS_BAR_PLUS 4073 { 4074 $$.r0 = 0; 4075 } 4076 | _PLUS_BAR_MINUS 4077 { 4078 $$.r0 = 1; 4079 } 4080 | _MINUS_BAR_PLUS 4081 { 4082 $$.r0 = 2; 4083 } 4084 | _MINUS_BAR_MINUS 4085 { 4086 $$.r0 = 3; 4087 } 4088 ; 4089 4090 plus_minus: 4091 PLUS 4092 { 4093 $$.r0 = 0; 4094 } 4095 | MINUS 4096 { 4097 $$.r0 = 1; 4098 } 4099 ; 4100 4101 rnd_op: 4102 LPAREN RNDH RPAREN 4103 { 4104 $$.r0 = 1; /* HL. */ 4105 $$.s0 = 0; /* s. */ 4106 $$.x0 = 0; /* x. */ 4107 $$.aop = 0; /* aop. */ 4108 } 4109 4110 | LPAREN TH RPAREN 4111 { 4112 $$.r0 = 1; /* HL. */ 4113 $$.s0 = 0; /* s. */ 4114 $$.x0 = 0; /* x. */ 4115 $$.aop = 1; /* aop. */ 4116 } 4117 4118 | LPAREN RNDL RPAREN 4119 { 4120 $$.r0 = 0; /* HL. */ 4121 $$.s0 = 0; /* s. */ 4122 $$.x0 = 0; /* x. */ 4123 $$.aop = 0; /* aop. */ 4124 } 4125 4126 | LPAREN TL RPAREN 4127 { 4128 $$.r0 = 0; /* HL. */ 4129 $$.s0 = 0; /* s. */ 4130 $$.x0 = 0; /* x. */ 4131 $$.aop = 1; 4132 } 4133 4134 | LPAREN RNDH COMMA R RPAREN 4135 { 4136 $$.r0 = 1; /* HL. */ 4137 $$.s0 = 1; /* s. */ 4138 $$.x0 = 0; /* x. */ 4139 $$.aop = 0; /* aop. */ 4140 } 4141 | LPAREN TH COMMA R RPAREN 4142 { 4143 $$.r0 = 1; /* HL. */ 4144 $$.s0 = 1; /* s. */ 4145 $$.x0 = 0; /* x. */ 4146 $$.aop = 1; /* aop. */ 4147 } 4148 | LPAREN RNDL COMMA R RPAREN 4149 { 4150 $$.r0 = 0; /* HL. */ 4151 $$.s0 = 1; /* s. */ 4152 $$.x0 = 0; /* x. */ 4153 $$.aop = 0; /* aop. */ 4154 } 4155 4156 | LPAREN TL COMMA R RPAREN 4157 { 4158 $$.r0 = 0; /* HL. */ 4159 $$.s0 = 1; /* s. */ 4160 $$.x0 = 0; /* x. */ 4161 $$.aop = 1; /* aop. */ 4162 } 4163 ; 4164 4165 b3_op: 4166 LPAREN LO RPAREN 4167 { 4168 $$.s0 = 0; /* s. */ 4169 $$.x0 = 0; /* HL. */ 4170 } 4171 | LPAREN HI RPAREN 4172 { 4173 $$.s0 = 0; /* s. */ 4174 $$.x0 = 1; /* HL. */ 4175 } 4176 | LPAREN LO COMMA R RPAREN 4177 { 4178 $$.s0 = 1; /* s. */ 4179 $$.x0 = 0; /* HL. */ 4180 } 4181 | LPAREN HI COMMA R RPAREN 4182 { 4183 $$.s0 = 1; /* s. */ 4184 $$.x0 = 1; /* HL. */ 4185 } 4186 ; 4187 4188 post_op: 4189 { 4190 $$.x0 = 2; 4191 } 4192 | _PLUS_PLUS 4193 { 4194 $$.x0 = 0; 4195 } 4196 | _MINUS_MINUS 4197 { 4198 $$.x0 = 1; 4199 } 4200 ; 4201 4202 /* Assignments, Macfuncs. */ 4203 4204 a_assign: 4205 REG_A ASSIGN 4206 { 4207 $$ = $1; 4208 } 4209 ; 4210 4211 a_minusassign: 4212 REG_A _MINUS_ASSIGN 4213 { 4214 $$ = $1; 4215 } 4216 ; 4217 4218 a_plusassign: 4219 REG_A _PLUS_ASSIGN 4220 { 4221 $$ = $1; 4222 } 4223 ; 4224 4225 assign_macfunc: 4226 REG ASSIGN REG_A 4227 { 4228 if (IS_A1 ($3) && IS_EVEN ($1)) 4229 return yyerror ("Cannot move A1 to even register"); 4230 else if (!IS_A1 ($3) && !IS_EVEN ($1)) 4231 return yyerror ("Cannot move A0 to odd register"); 4232 4233 $$.w = 1; 4234 $$.P = 1; 4235 $$.n = IS_A1 ($3); 4236 $$.op = 3; 4237 $$.dst = $1; 4238 $$.s0.regno = 0; 4239 $$.s1.regno = 0; 4240 } 4241 | a_macfunc 4242 { 4243 $$ = $1; 4244 $$.w = 0; $$.P = 0; 4245 $$.dst.regno = 0; 4246 } 4247 | REG ASSIGN LPAREN a_macfunc RPAREN 4248 { 4249 if ($4.n && IS_EVEN ($1)) 4250 return yyerror ("Cannot move A1 to even register"); 4251 else if (!$4.n && !IS_EVEN ($1)) 4252 return yyerror ("Cannot move A0 to odd register"); 4253 4254 $$ = $4; 4255 $$.w = 1; 4256 $$.P = 1; 4257 $$.dst = $1; 4258 } 4259 4260 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN 4261 { 4262 if ($4.n && !IS_H ($1)) 4263 return yyerror ("Cannot move A1 to low half of register"); 4264 else if (!$4.n && IS_H ($1)) 4265 return yyerror ("Cannot move A0 to high half of register"); 4266 4267 $$ = $4; 4268 $$.w = 1; 4269 $$.P = 0; 4270 $$.dst = $1; 4271 } 4272 4273 | HALF_REG ASSIGN REG_A 4274 { 4275 if (IS_A1 ($3) && !IS_H ($1)) 4276 return yyerror ("Cannot move A1 to low half of register"); 4277 else if (!IS_A1 ($3) && IS_H ($1)) 4278 return yyerror ("Cannot move A0 to high half of register"); 4279 4280 $$.w = 1; 4281 $$.P = 0; 4282 $$.n = IS_A1 ($3); 4283 $$.op = 3; 4284 $$.dst = $1; 4285 $$.s0.regno = 0; 4286 $$.s1.regno = 0; 4287 } 4288 ; 4289 4290 a_macfunc: 4291 a_assign multiply_halfregs 4292 { 4293 $$.n = IS_A1 ($1); 4294 $$.op = 0; 4295 $$.s0 = $2.s0; 4296 $$.s1 = $2.s1; 4297 } 4298 | a_plusassign multiply_halfregs 4299 { 4300 $$.n = IS_A1 ($1); 4301 $$.op = 1; 4302 $$.s0 = $2.s0; 4303 $$.s1 = $2.s1; 4304 } 4305 | a_minusassign multiply_halfregs 4306 { 4307 $$.n = IS_A1 ($1); 4308 $$.op = 2; 4309 $$.s0 = $2.s0; 4310 $$.s1 = $2.s1; 4311 } 4312 ; 4313 4314 multiply_halfregs: 4315 HALF_REG STAR HALF_REG 4316 { 4317 if (IS_DREG ($1) && IS_DREG ($3)) 4318 { 4319 $$.s0 = $1; 4320 $$.s1 = $3; 4321 } 4322 else 4323 return yyerror ("Dregs expected"); 4324 } 4325 ; 4326 4327 cc_op: 4328 ASSIGN 4329 { 4330 $$.r0 = 0; 4331 } 4332 | _BAR_ASSIGN 4333 { 4334 $$.r0 = 1; 4335 } 4336 | _AMPERSAND_ASSIGN 4337 { 4338 $$.r0 = 2; 4339 } 4340 | _CARET_ASSIGN 4341 { 4342 $$.r0 = 3; 4343 } 4344 ; 4345 4346 ccstat: 4347 CCREG cc_op STATUS_REG 4348 { 4349 $$.r0 = $3.regno; 4350 $$.x0 = $2.r0; 4351 $$.s0 = 0; 4352 } 4353 | CCREG cc_op V 4354 { 4355 $$.r0 = 0x18; 4356 $$.x0 = $2.r0; 4357 $$.s0 = 0; 4358 } 4359 | STATUS_REG cc_op CCREG 4360 { 4361 $$.r0 = $1.regno; 4362 $$.x0 = $2.r0; 4363 $$.s0 = 1; 4364 } 4365 | V cc_op CCREG 4366 { 4367 $$.r0 = 0x18; 4368 $$.x0 = $2.r0; 4369 $$.s0 = 1; 4370 } 4371 ; 4372 4373 /* Expressions and Symbols. */ 4374 4375 symbol: SYMBOL 4376 { 4377 Expr_Node_Value val; 4378 val.s_value = S_GET_NAME($1); 4379 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL); 4380 } 4381 ; 4382 4383 any_gotrel: 4384 GOT 4385 { $$ = BFD_RELOC_BFIN_GOT; } 4386 | GOT17M4 4387 { $$ = BFD_RELOC_BFIN_GOT17M4; } 4388 | FUNCDESC_GOT17M4 4389 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; } 4390 ; 4391 4392 got: symbol AT any_gotrel 4393 { 4394 Expr_Node_Value val; 4395 val.i_value = $3; 4396 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL); 4397 } 4398 ; 4399 4400 got_or_expr: got 4401 { 4402 $$ = $1; 4403 } 4404 | expr 4405 { 4406 $$ = $1; 4407 } 4408 ; 4409 4410 pltpc : 4411 symbol AT PLTPC 4412 { 4413 $$ = $1; 4414 } 4415 ; 4416 4417 eterm: NUMBER 4418 { 4419 Expr_Node_Value val; 4420 val.i_value = $1; 4421 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL); 4422 } 4423 | symbol 4424 { 4425 $$ = $1; 4426 } 4427 | LPAREN expr_1 RPAREN 4428 { 4429 $$ = $2; 4430 } 4431 | TILDA expr_1 4432 { 4433 $$ = unary (Expr_Op_Type_COMP, $2); 4434 } 4435 | MINUS expr_1 %prec TILDA 4436 { 4437 $$ = unary (Expr_Op_Type_NEG, $2); 4438 } 4439 ; 4440 4441 expr: expr_1 4442 { 4443 $$ = $1; 4444 } 4445 ; 4446 4447 expr_1: expr_1 STAR expr_1 4448 { 4449 $$ = binary (Expr_Op_Type_Mult, $1, $3); 4450 } 4451 | expr_1 SLASH expr_1 4452 { 4453 $$ = binary (Expr_Op_Type_Div, $1, $3); 4454 } 4455 | expr_1 PERCENT expr_1 4456 { 4457 $$ = binary (Expr_Op_Type_Mod, $1, $3); 4458 } 4459 | expr_1 PLUS expr_1 4460 { 4461 $$ = binary (Expr_Op_Type_Add, $1, $3); 4462 } 4463 | expr_1 MINUS expr_1 4464 { 4465 $$ = binary (Expr_Op_Type_Sub, $1, $3); 4466 } 4467 | expr_1 LESS_LESS expr_1 4468 { 4469 $$ = binary (Expr_Op_Type_Lshift, $1, $3); 4470 } 4471 | expr_1 GREATER_GREATER expr_1 4472 { 4473 $$ = binary (Expr_Op_Type_Rshift, $1, $3); 4474 } 4475 | expr_1 AMPERSAND expr_1 4476 { 4477 $$ = binary (Expr_Op_Type_BAND, $1, $3); 4478 } 4479 | expr_1 CARET expr_1 4480 { 4481 $$ = binary (Expr_Op_Type_LOR, $1, $3); 4482 } 4483 | expr_1 BAR expr_1 4484 { 4485 $$ = binary (Expr_Op_Type_BOR, $1, $3); 4486 } 4487 | eterm 4488 { 4489 $$ = $1; 4490 } 4491 ; 4492 4493 4494 %% 4495 4496 EXPR_T 4497 mkexpr (int x, SYMBOL_T s) 4498 { 4499 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell)); 4500 e->value = x; 4501 EXPR_SYMBOL(e) = s; 4502 return e; 4503 } 4504 4505 static int 4506 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned) 4507 { 4508 int umax = (1 << sz) - 1; 4509 int min = -1 << (sz - 1); 4510 int max = (1 << (sz - 1)) - 1; 4511 4512 int v = (EXPR_VALUE (exp)) & 0xffffffff; 4513 4514 if ((v % mul) != 0) 4515 { 4516 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul); 4517 return 0; 4518 } 4519 4520 v /= mul; 4521 4522 if (sign) 4523 v = -v; 4524 4525 if (issigned) 4526 { 4527 if (v >= min && v <= max) return 1; 4528 4529 #ifdef DEBUG 4530 fprintf(stderr, "signed value %lx out of range\n", v * mul); 4531 #endif 4532 return 0; 4533 } 4534 if (v <= umax && v >= 0) 4535 return 1; 4536 #ifdef DEBUG 4537 fprintf(stderr, "unsigned value %lx out of range\n", v * mul); 4538 #endif 4539 return 0; 4540 } 4541 4542 /* Return the expression structure that allows symbol operations. 4543 If the left and right children are constants, do the operation. */ 4544 static Expr_Node * 4545 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y) 4546 { 4547 Expr_Node_Value val; 4548 4549 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant) 4550 { 4551 switch (op) 4552 { 4553 case Expr_Op_Type_Add: 4554 x->value.i_value += y->value.i_value; 4555 break; 4556 case Expr_Op_Type_Sub: 4557 x->value.i_value -= y->value.i_value; 4558 break; 4559 case Expr_Op_Type_Mult: 4560 x->value.i_value *= y->value.i_value; 4561 break; 4562 case Expr_Op_Type_Div: 4563 if (y->value.i_value == 0) 4564 error ("Illegal Expression: Division by zero."); 4565 else 4566 x->value.i_value /= y->value.i_value; 4567 break; 4568 case Expr_Op_Type_Mod: 4569 x->value.i_value %= y->value.i_value; 4570 break; 4571 case Expr_Op_Type_Lshift: 4572 x->value.i_value <<= y->value.i_value; 4573 break; 4574 case Expr_Op_Type_Rshift: 4575 x->value.i_value >>= y->value.i_value; 4576 break; 4577 case Expr_Op_Type_BAND: 4578 x->value.i_value &= y->value.i_value; 4579 break; 4580 case Expr_Op_Type_BOR: 4581 x->value.i_value |= y->value.i_value; 4582 break; 4583 case Expr_Op_Type_BXOR: 4584 x->value.i_value ^= y->value.i_value; 4585 break; 4586 case Expr_Op_Type_LAND: 4587 x->value.i_value = x->value.i_value && y->value.i_value; 4588 break; 4589 case Expr_Op_Type_LOR: 4590 x->value.i_value = x->value.i_value || y->value.i_value; 4591 break; 4592 4593 default: 4594 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__); 4595 } 4596 return x; 4597 } 4598 /* Canonicalize order to EXPR OP CONSTANT. */ 4599 if (x->type == Expr_Node_Constant) 4600 { 4601 Expr_Node *t = x; 4602 x = y; 4603 y = t; 4604 } 4605 /* Canonicalize subtraction of const to addition of negated const. */ 4606 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant) 4607 { 4608 op = Expr_Op_Type_Add; 4609 y->value.i_value = -y->value.i_value; 4610 } 4611 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop 4612 && x->Right_Child->type == Expr_Node_Constant) 4613 { 4614 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add) 4615 { 4616 x->Right_Child->value.i_value += y->value.i_value; 4617 return x; 4618 } 4619 } 4620 4621 /* Create a new expression structure. */ 4622 val.op_value = op; 4623 return Expr_Node_Create (Expr_Node_Binop, val, x, y); 4624 } 4625 4626 static Expr_Node * 4627 unary (Expr_Op_Type op, Expr_Node *x) 4628 { 4629 if (x->type == Expr_Node_Constant) 4630 { 4631 switch (op) 4632 { 4633 case Expr_Op_Type_NEG: 4634 x->value.i_value = -x->value.i_value; 4635 break; 4636 case Expr_Op_Type_COMP: 4637 x->value.i_value = ~x->value.i_value; 4638 break; 4639 default: 4640 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__); 4641 } 4642 return x; 4643 } 4644 else 4645 { 4646 /* Create a new expression structure. */ 4647 Expr_Node_Value val; 4648 val.op_value = op; 4649 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL); 4650 } 4651 } 4652 4653 int debug_codeselection = 0; 4654 static void 4655 notethat (char *format, ...) 4656 { 4657 va_list ap; 4658 va_start (ap, format); 4659 if (debug_codeselection) 4660 { 4661 vfprintf (errorf, format, ap); 4662 } 4663 va_end (ap); 4664 } 4665 4666 #ifdef TEST 4667 main (int argc, char **argv) 4668 { 4669 yyparse(); 4670 } 4671 #endif 4672 4673
