| /external/swiftshader/third_party/subzero/crosstest/ |
| test_calling_conv.cpp | 49 v4f32 arg10 = {22, 23, 24, 25}; local
54 arg6, arg7, arg8, arg9, arg10,
81 v4f32 arg10, int arg11, v4f32 arg12) {
|
| /external/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/ |
| stratified-attrs-indexing.ll | 13 i32* %arg6, i32* %arg7, i32* %arg8, i32* %arg9, i32* %arg10,
|
| /external/libchrome/base/third_party/valgrind/ |
| valgrind.h | [all...] |
| /external/regex-re2/util/ |
| valgrind.h | [all...] |
| /external/valgrind/include/ |
| valgrind.h | [all...] |
| /external/v8/src/third_party/valgrind/ |
| valgrind.h | [all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/Ia32/ |
| EbcSupport.c | 196 @param Arg10 The 10th argument.
220 IN UINTN Arg10,
296 *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) Arg10;
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/X64/ |
| EbcSupport.c | 141 @param Arg10 The 10th argument.
165 IN UINTN Arg10,
241 PushU64 (&VmContext, (UINT64) Arg10);
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| sgpr-copy.ll | 14 define amdgpu_ps void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
38 define amdgpu_ps void @phi2(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
159 define amdgpu_ps void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
230 define amdgpu_ps void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
294 define amdgpu_ps void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
324 define amdgpu_ps void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
|
| schedule-kernel-arg-loads.ll | 31 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
|
| si-lod-bias.ll | 9 define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) {
|
| si-scheduler.ll | 19 define amdgpu_ps void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
|
| vgpr-spill-emergency-stack-slot.ll | 29 define amdgpu_vs void @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
|
| si-sgpr-spill.ll | 25 define amdgpu_ps void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/Ipf/ |
| EbcSupport.c | 105 UINT64 Arg10;
130 Arg10 = VA_ARG (List, UINT64);
158 // arg10
199 PushU64 (&VmContext, Arg10);
|
| /test/vts/compilation_tools/vtsc/test/golden/FUZZER/ |
| Context.fuzzer.cpp | 769 uint64_t arg10; local
770 memcpy(&arg10, data, type_size10);
773 renderscript->allocation3DRead(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10);
883 uint32_t arg10; local
884 memcpy(&arg10, data, type_size10);
894 renderscript->allocationCopy2DRange(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11);
970 uint32_t arg10; local
971 memcpy(&arg10, data, type_size10);
988 renderscript->allocationCopy3DRange(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12);
[all...] |
| /external/syslinux/efi64/include/efi/x86_64/ |
| efibind.h | 335 UINT64 arg8, UINT64 arg9, UINT64 arg10);
|
| /external/syslinux/gnu-efi/gnu-efi-3.0/inc/x86_64/ |
| efibind.h | 335 UINT64 arg8, UINT64 arg9, UINT64 arg10);
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| 8bit.pnacl.ll | 522 define internal i32 @testPhi8(i32 %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) {
536 %trunc10 = trunc i32 %arg10 to i8
|
| /external/valgrind/VEX/priv/ |
| ir_defs.c | [all...] |
