1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4 ; This shader has the potential to generated illegal VGPR to SGPR copies if 5 ; the wrong register class is used for the REG_SEQUENCE instructions. 6 7 ; CHECK: {{^}}main: 8 ; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf 9 define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) { 10 main_body: 11 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 12 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 13 %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) 14 %tmp22 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0 15 %tmp23 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp22, !tbaa !0 16 %tmp24 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0 17 %tmp25 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp24, !tbaa !0 18 %tmp26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg3, <2 x i32> %arg5) 19 %tmp27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg3, <2 x i32> %arg5) 20 %tmp28 = bitcast float %tmp21 to i32 21 %tmp29 = bitcast float %tmp26 to i32 22 %tmp30 = bitcast float %tmp27 to i32 23 %tmp31 = insertelement <4 x i32> undef, i32 %tmp28, i32 0 24 %tmp32 = insertelement <4 x i32> %tmp31, i32 %tmp29, i32 1 25 %tmp33 = insertelement <4 x i32> %tmp32, i32 %tmp30, i32 2 26 %tmp34 = insertelement <4 x i32> %tmp33, i32 undef, i32 3 27 %tmp25.bc = bitcast <16 x i8> %tmp25 to <4 x i32> 28 %tmp35 = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> %tmp34, <8 x i32> %tmp23, <4 x i32> %tmp25.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 29 %tmp36 = extractelement <4 x float> %tmp35, i32 0 30 %tmp37 = extractelement <4 x float> %tmp35, i32 1 31 %tmp38 = extractelement <4 x float> %tmp35, i32 2 32 %tmp39 = extractelement <4 x float> %tmp35, i32 3 33 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %tmp36, float %tmp37, float %tmp38, float %tmp39) 34 ret void 35 } 36 37 ; Function Attrs: nounwind readnone 38 declare float @llvm.SI.load.const(<16 x i8>, i32) #1 39 40 ; Function Attrs: nounwind readnone 41 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 42 43 declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 44 45 46 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 47 48 49 attributes #1 = { nounwind readnone } 50 51 !0 = !{!1, !1, i64 0, i32 1} 52 !1 = !{!"const", null} 53
