| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 981 Instr Assembler::ImmCondBranch(int imm19) {
982 CHECK(is_int19(imm19));
983 return truncate_to_int19(imm19) << ImmCondBranch_offset;
987 Instr Assembler::ImmCmpBranch(int imm19) {
988 CHECK(is_int19(imm19));
989 return truncate_to_int19(imm19) << ImmCmpBranch_offset;
1061 Instr Assembler::ImmLLiteral(int imm19) {
1062 CHECK(is_int19(imm19));
1063 return truncate_to_int19(imm19) << ImmLLiteral_offset;
[all...] |
| assembler-arm64.cc | [all...] |
| assembler-arm64.h | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | 503 void b(int64_t imm19, Condition cond);
515 void cbz(const Register& rt, int64_t imm19);
521 void cbnz(const Register& rt, int64_t imm19);
[all...] |
| assembler-aarch64.cc | 122 ptrdiff_t imm19 = ldr->GetImmLLiteral(); local
123 VIXL_ASSERT(imm19 <= 0);
124 done = (imm19 == 0);
125 offset += imm19 * kLiteralEntrySize;
201 void Assembler::b(int64_t imm19, Condition cond) {
202 Emit(B_cond | ImmCondBranch(imm19) | cond);
230 void Assembler::cbz(const Register& rt, int64_t imm19) {
231 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
242 void Assembler::cbnz(const Register& rt, int64_t imm19) {
243 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt))
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.td | 792 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
793 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
796 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
797 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
800 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
801 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
[all...] |
| SparcInstrFormats.td | 75 bits<19> imm19;
84 let Inst{18-0} = imm19;
|
| SparcInstr64Bit.td | 312 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 584 void Mips64Assembler::Lwpc(GpuRegister rs, uint32_t imm19) {
585 CHECK(IsUint<19>(imm19)) << imm19;
586 EmitI21(0x3B, rs, (0x01 << 19) | imm19);
589 void Mips64Assembler::Lwupc(GpuRegister rs, uint32_t imm19) {
590 CHECK(IsUint<19>(imm19)) << imm19;
591 EmitI21(0x3B, rs, (0x02 << 19) | imm19);
697 void Mips64Assembler::Addiupc(GpuRegister rs, uint32_t imm19) {
698 CHECK(IsUint<19>(imm19)) << imm19
[all...] |
| assembler_mips64.h | 517 void Lwpc(GpuRegister rs, uint32_t imm19);
518 void Lwupc(GpuRegister rs, uint32_t imm19); // MIPS64
547 void Addiupc(GpuRegister rs, uint32_t imm19);
[all...] |
| /external/v8/src/mips/ |
| disasm-mips.cc | 330 int32_t imm19 = instr->Imm19Value(); local
332 imm19 <<= (32 - kImm19Bits);
333 imm19 >>= (32 - kImm19Bits);
334 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19);
604 DCHECK(STRING_STARTS_WITH(format, "imm19"));
[all...] |
| simulator-mips.cc | [all...] |
| assembler-mips.cc | [all...] |
| assembler-mips.h | 785 void addiupc(Register rs, int32_t imm19);
[all...] |
| /external/vixl/doc/aarch64/ |
| supported-instructions-aarch64.md | 112 void b(int imm19, Condition cond)
223 void cbnz(const Register& rt, int imm19)
237 void cbz(const Register& rt, int imm19)
603 Load integer or FP register from pc + imm19 << 2.
605 void ldr(const CPURegister& rt, int imm19)
657 Load word with sign extension from pc + imm19 << 2.
659 void ldrsw(const Register& xt, int imm19)
912 Prefetch from pc + imm19 << 2.
914 void prfm(PrefetchOperation op, int imm19)
[all...] |
| /external/v8/src/mips64/ |
| disasm-mips64.cc | 333 int32_t imm19 = instr->Imm19Value(); local
335 imm19 <<= (32 - kImm19Bits);
336 imm19 >>= (32 - kImm19Bits);
337 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19);
620 DCHECK(STRING_STARTS_WITH(format, "imm19"));
[all...] |
| simulator-mips64.cc | [all...] |
| assembler-mips64.cc | [all...] |
| assembler-mips64.h | 830 void addiupc(Register rs, int32_t imm19);
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MachObjectWriter.cpp | 171 // imm19 relocations are for conditional branches, which require
|
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | 5080 UInt imm19 = INSN(23,5); local
5786 UInt imm19 = INSN(23,5); local
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.cc | 816 void MipsAssembler::Lwpc(Register rs, uint32_t imm19) {
818 CHECK(IsUint<19>(imm19)) << imm19;
819 DsFsmInstrNop(EmitI21(0x3B, rs, (0x01 << 19) | imm19));
[all...] |
| assembler_mips.h | 280 void Lwpc(Register rs, uint32_t imm19); // R6
333 void Addiupc(Register rs, uint32_t imm19); // R6
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-opc.c | 145 { 5, 19 }, /* imm19: e.g. in CBZ. */
[all...] |
| /toolchain/binutils/binutils-2.25/gold/ |
| aarch64.cc | [all...] |
