| /toolchain/binutils/binutils-2.25/opcodes/ |
| m10200-opc.c | 85 #define IMM24 (IMM16_MEM+1)
89 #define IMM24_PCREL (IMM24+1)
179 { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
186 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
193 { "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
200 { "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
205 { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
207 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
211 { "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
214 { "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}
[all...] |
| m10300-opc.c | 301 #define IMM24 (SD24+1)
306 #define SIMM24 (IMM24+1)
527 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
529 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
533 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
534 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
570 { "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}},
580 { "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
599 { "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
609 { "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}
[all...] |
| tic30-dis.c | 154 if (current_optab->operand_types[0] & Imm24)
609 if (insn->tm->operand_types[0] & Imm24)
|
| ChangeLog-9297 | [all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| elf-m10200.c | 545 * Most instructions which accept imm24 can relax to imm16 2 bytes
551 abs24, imm24, d24 all look the same at the reloc level. It
961 /* mov imm24,dn -> mov imm16,dn */
996 /* mov imm24,an -> mov imm16,an
997 cmp imm24,an -> cmp imm16,an
1047 /* cmp imm24,dn -> cmp imm16,dn
1050 add imm24,dn -> add imm16,dn
1051 add imm24,an -> add imm16,an
1052 sub imm24,dn -> sub imm16,dn
1053 sub imm24,an -> sub imm16,a
[all...] |
| ChangeLog-9697 | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| tic30.h | 199 #define Imm24 0x0100
317 { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt },
318 { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt },
319 { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt },
554 { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt },
[all...] |
| h8300.h | 279 #define IMM24LIST IMM24, DATA5
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.cc | 896 DCHECK_EQ(5 * B25, instr & 7 * B25); // b, bl, or blx imm24
984 DCHECK_EQ(5 * B25, instr & 7 * B25); // b, bl, or blx imm24
993 int imm24 = imm26 >> 2; local
994 DCHECK(is_int24(imm24));
995 instr_at_put(pos, instr | (imm24 & kImm24Mask));
1452 int imm24 = branch_offset >> 2; local
1465 int imm24 = branch_offset >> 2; local
1473 int imm24 = branch_offset >> 2; local
[all...] |
| assembler-arm.h | [all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitLir.c | 138 /* IT + imm24 */
142 /* imm24 */
144 /* BL + imm24 */
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-tic30.c | 634 current_op->op_type = Disp | Abs24 | Imm16 | Imm24;
[all...] |
| /external/valgrind/coregrind/m_syswrap/ |
| syswrap-main.c | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.cpp | 520 // Checks that Offset can fit in imm24 constant of branch (b) instruction.
[all...] |
