| /external/llvm/test/TableGen/ |
| MultiPat.td | 73 def REGCLASS : RegisterClass<[], []>;
98 !subst(REGCLASS, VR128,
103 !subst(REGCLASS, VR128,
116 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],
117 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
118 (MNEMONIC REGCLASS:$dst, REGCLASS:$src)]]>
[all...] |
| TargetInstrSpec.td | 70 def REGCLASS : RegisterClass<[], []>;
91 !subst(REGCLASS, VR128, Decls.operand))))>;
98 !subst(REGCLASS, VR128, Decls.operand))))>;
102 [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
|
| /external/swiftshader/third_party/LLVM/test/TableGen/ |
| MultiPat.td | 73 def REGCLASS : RegisterClass<[], []>;
98 !subst(REGCLASS, VR128,
103 !subst(REGCLASS, VR128,
116 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],
117 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
118 (MNEMONIC REGCLASS:$dst, REGCLASS:$src)]]>
[all...] |
| TargetInstrSpec.td | 65 def REGCLASS : RegisterClass<[], []>;
86 !subst(REGCLASS, VR128, Decls.operand))))>;
93 !subst(REGCLASS, VR128, Decls.operand))))>;
97 [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.td | [all...] |
| NVPTXVector.td | 239 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
241 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a, regclass:$b),
243 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
253 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
255 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrArithmetic.td | 503 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
515 /// RegClass - This is the register class associated with this type. For
517 RegisterClass RegClass = regclass;
606 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
610 // just a regclass (no eflags) as a result.
613 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
614 [(set typeinfo.RegClass:$dst,
615 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| TargetInstrInfo.cpp | 36 short RegClass = MCID.OpInfo[OpNum].RegClass;
38 return TRI->getPointerRegClass(RegClass);
41 if (RegClass < 0)
45 return TRI->getRegClass(RegClass);
|
| /external/llvm/test/CodeGen/X86/ |
| coalescer-subreg.ll | 2 ; This used to crash when coalescing a regclass like GR16 which did not support
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| RegisterScavenging.h | 107 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
118 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
120 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
121 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /external/swiftshader/third_party/subzero/src/ |
| IceTypes.h | 31 /// RegClass indicates the physical register class that a Variable may be
36 enum RegClass : uint8_t {
46 static_assert(RC_Target == static_cast<RegClass>(IceType_NUM),
86 const char *regClassString(RegClass C);
|
| IceTargetLoweringX86RegClass.h | 23 // Extend enum RegClass with x86-specific register classes.
|
| /external/llvm/lib/Target/X86/ |
| X86InstrArithmetic.td | 550 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
563 /// RegClass - This is the register class associated with this type. For
565 RegisterClass RegClass = regclass;
658 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
668 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
672 // both a regclass and EFLAGS as a result.
675 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
98 assert(RegClass && "Cannot create register without RegClass!");
99 assert(RegClass->isAllocatable() &&
100 "Virtual register RegClass must be allocatable.");
109 VRegInfo[Reg].first = RegClass;
|
| /external/libunwind_llvm/src/ |
| Unwind-EHABI.cpp | 754 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
757 _LIBUNWIND_TRACE_API("_Unwind_VRS_Set(context=%p, regclass=%d, reg=%d, "
759 static_cast<void *>(context), regclass, regno,
763 switch (regclass) {
813 _Unwind_VRS_RegClass regclass, uint32_t regno,
817 switch (regclass) {
866 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
870 _Unwind_VRS_Get_Internal(context, regclass, regno, representation,
872 _LIBUNWIND_TRACE_API("_Unwind_VRS_Get(context=%p, regclass=%d, reg=%d, "
874 static_cast<void *>(context), regclass, regno
[all...] |
| /prebuilts/ndk/r11/sources/cxx-stl/llvm-libc++abi/libcxxabi/src/Unwind/ |
| Unwind-EHABI.cpp | 783 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
786 _LIBUNWIND_TRACE_API("_Unwind_VRS_Set(context=%p, regclass=%d, reg=%d, "
788 static_cast<void *>(context), regclass, regno,
792 switch (regclass) {
836 _Unwind_VRS_RegClass regclass, uint32_t regno,
840 switch (regclass) {
884 _Unwind_VRS_RegClass regclass,
889 _Unwind_VRS_Get_Internal(context, regclass, regno, representation,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 52 isARMLowRegister(SrcReg))) && "Unknown regclass!");
81 isARMLowRegister(DestReg))) && "Unknown regclass!");
|
| /prebuilts/ndk/r10/sources/cxx-stl/llvm-libc++/gabi++/include/ |
| unwind-arm.h | 124 _Unwind_VRS_RegClass regclass,
130 _Unwind_VRS_RegClass regclass,
|
| /prebuilts/ndk/r11/sources/cxx-stl/gabi++/include/ |
| unwind-arm.h | 123 _Unwind_VRS_RegClass regclass,
129 _Unwind_VRS_RegClass regclass,
|
| /prebuilts/ndk/r13/sources/cxx-stl/gabi++/include/ |
| unwind-arm.h | 123 _Unwind_VRS_RegClass regclass,
129 _Unwind_VRS_RegClass regclass,
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 114 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
143 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
146 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/ |
| inline-asm.ll | 24 ; Target "z" for P0, P1, P2. This is not a real regclass
|
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 130 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
159 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
161 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
162 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 130 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
159 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
161 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
162 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 130 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
159 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
161 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
162 return scavengeRegister(RegClass, MBBI, SPAdj);
|
