1 /* move-wide/16 vAAAA, vBBBB */ 2 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 3 lhu a3, 4(rPC) # a3 <- BBBB 4 lhu a2, 2(rPC) # a2 <- AAAA 5 GET_VREG_WIDE a0, a3 # a0 <- vBBBB 6 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 7 GET_INST_OPCODE v0 # extract opcode from rINST 8 SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB 9 GOTO_OPCODE v0 # jump to next instruction 10
