1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef KFD_IOCTL_H_INCLUDED 20 #define KFD_IOCTL_H_INCLUDED 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define KFD_IOCTL_MAJOR_VERSION 1 24 #define KFD_IOCTL_MINOR_VERSION 1 25 struct kfd_ioctl_get_version_args { 26 uint32_t major_version; 27 uint32_t minor_version; 28 }; 29 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0 30 #define KFD_IOC_QUEUE_TYPE_SDMA 1 31 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2 32 #define KFD_MAX_QUEUE_PERCENTAGE 100 33 #define KFD_MAX_QUEUE_PRIORITY 15 34 struct kfd_ioctl_create_queue_args { 35 uint64_t ring_base_address; 36 uint64_t write_pointer_address; 37 uint64_t read_pointer_address; 38 uint64_t doorbell_offset; 39 uint32_t ring_size; 40 uint32_t gpu_id; 41 uint32_t queue_type; 42 uint32_t queue_percentage; 43 uint32_t queue_priority; 44 uint32_t queue_id; 45 uint64_t eop_buffer_address; 46 uint64_t eop_buffer_size; 47 uint64_t ctx_save_restore_address; 48 uint64_t ctx_save_restore_size; 49 }; 50 struct kfd_ioctl_destroy_queue_args { 51 uint32_t queue_id; 52 uint32_t pad; 53 }; 54 struct kfd_ioctl_update_queue_args { 55 uint64_t ring_base_address; 56 uint32_t queue_id; 57 uint32_t ring_size; 58 uint32_t queue_percentage; 59 uint32_t queue_priority; 60 }; 61 #define KFD_IOC_CACHE_POLICY_COHERENT 0 62 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 63 struct kfd_ioctl_set_memory_policy_args { 64 uint64_t alternate_aperture_base; 65 uint64_t alternate_aperture_size; 66 uint32_t gpu_id; 67 uint32_t default_policy; 68 uint32_t alternate_policy; 69 uint32_t pad; 70 }; 71 struct kfd_ioctl_get_clock_counters_args { 72 uint64_t gpu_clock_counter; 73 uint64_t cpu_clock_counter; 74 uint64_t system_clock_counter; 75 uint64_t system_clock_freq; 76 uint32_t gpu_id; 77 uint32_t pad; 78 }; 79 #define NUM_OF_SUPPORTED_GPUS 7 80 struct kfd_process_device_apertures { 81 uint64_t lds_base; 82 uint64_t lds_limit; 83 uint64_t scratch_base; 84 uint64_t scratch_limit; 85 uint64_t gpuvm_base; 86 uint64_t gpuvm_limit; 87 uint32_t gpu_id; 88 uint32_t pad; 89 }; 90 struct kfd_ioctl_get_process_apertures_args { 91 struct kfd_process_device_apertures process_apertures[NUM_OF_SUPPORTED_GPUS]; 92 uint32_t num_of_nodes; 93 uint32_t pad; 94 }; 95 #define MAX_ALLOWED_NUM_POINTS 100 96 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 97 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 98 struct kfd_ioctl_dbg_register_args { 99 uint32_t gpu_id; 100 uint32_t pad; 101 }; 102 struct kfd_ioctl_dbg_unregister_args { 103 uint32_t gpu_id; 104 uint32_t pad; 105 }; 106 struct kfd_ioctl_dbg_address_watch_args { 107 uint64_t content_ptr; 108 uint32_t gpu_id; 109 uint32_t buf_size_in_bytes; 110 }; 111 struct kfd_ioctl_dbg_wave_control_args { 112 uint64_t content_ptr; 113 uint32_t gpu_id; 114 uint32_t buf_size_in_bytes; 115 }; 116 #define KFD_IOC_EVENT_SIGNAL 0 117 #define KFD_IOC_EVENT_NODECHANGE 1 118 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 119 #define KFD_IOC_EVENT_HW_EXCEPTION 3 120 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 121 #define KFD_IOC_EVENT_DEBUG_EVENT 5 122 #define KFD_IOC_EVENT_PROFILE_EVENT 6 123 #define KFD_IOC_EVENT_QUEUE_EVENT 7 124 #define KFD_IOC_EVENT_MEMORY 8 125 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 126 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 127 #define KFD_IOC_WAIT_RESULT_FAIL 2 128 #define KFD_SIGNAL_EVENT_LIMIT 256 129 struct kfd_ioctl_create_event_args { 130 uint64_t event_page_offset; 131 uint32_t event_trigger_data; 132 uint32_t event_type; 133 uint32_t auto_reset; 134 uint32_t node_id; 135 uint32_t event_id; 136 uint32_t event_slot_index; 137 }; 138 struct kfd_ioctl_destroy_event_args { 139 uint32_t event_id; 140 uint32_t pad; 141 }; 142 struct kfd_ioctl_set_event_args { 143 uint32_t event_id; 144 uint32_t pad; 145 }; 146 struct kfd_ioctl_reset_event_args { 147 uint32_t event_id; 148 uint32_t pad; 149 }; 150 struct kfd_memory_exception_failure { 151 uint32_t NotPresent; 152 uint32_t ReadOnly; 153 uint32_t NoExecute; 154 uint32_t pad; 155 }; 156 struct kfd_hsa_memory_exception_data { 157 struct kfd_memory_exception_failure failure; 158 uint64_t va; 159 uint32_t gpu_id; 160 uint32_t pad; 161 }; 162 struct kfd_event_data { 163 union { 164 struct kfd_hsa_memory_exception_data memory_exception_data; 165 }; 166 uint64_t kfd_event_data_ext; 167 uint32_t event_id; 168 uint32_t pad; 169 }; 170 struct kfd_ioctl_wait_events_args { 171 uint64_t events_ptr; 172 uint32_t num_events; 173 uint32_t wait_for_all; 174 uint32_t timeout; 175 uint32_t wait_result; 176 }; 177 #define AMDKFD_IOCTL_BASE 'K' 178 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 179 #define AMDKFD_IOR(nr,type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 180 #define AMDKFD_IOW(nr,type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 181 #define AMDKFD_IOWR(nr,type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 182 #define AMDKFD_IOC_GET_VERSION AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 183 #define AMDKFD_IOC_CREATE_QUEUE AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 184 #define AMDKFD_IOC_DESTROY_QUEUE AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 185 #define AMDKFD_IOC_SET_MEMORY_POLICY AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 186 #define AMDKFD_IOC_GET_CLOCK_COUNTERS AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 187 #define AMDKFD_IOC_GET_PROCESS_APERTURES AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 188 #define AMDKFD_IOC_UPDATE_QUEUE AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 189 #define AMDKFD_IOC_CREATE_EVENT AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 190 #define AMDKFD_IOC_DESTROY_EVENT AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 191 #define AMDKFD_IOC_SET_EVENT AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 192 #define AMDKFD_IOC_RESET_EVENT AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 193 #define AMDKFD_IOC_WAIT_EVENTS AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 194 #define AMDKFD_IOC_DBG_REGISTER AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 195 #define AMDKFD_IOC_DBG_UNREGISTER AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 196 #define AMDKFD_IOC_DBG_ADDRESS_WATCH AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 197 #define AMDKFD_IOC_DBG_WAVE_CONTROL AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 198 #define AMDKFD_COMMAND_START 0x01 199 #define AMDKFD_COMMAND_END 0x11 200 #endif 201
