1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef VIRTIO_GPU_HW_H 20 #define VIRTIO_GPU_HW_H 21 #include <linux/types.h> 22 #define VIRTIO_GPU_F_VIRGL 0 23 enum virtio_gpu_ctrl_type { 24 VIRTIO_GPU_UNDEFINED = 0, 25 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 26 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 27 VIRTIO_GPU_CMD_RESOURCE_UNREF, 28 VIRTIO_GPU_CMD_SET_SCANOUT, 29 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 30 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 31 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 32 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 33 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 34 VIRTIO_GPU_CMD_GET_CAPSET, 35 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 36 VIRTIO_GPU_CMD_CTX_DESTROY, 37 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 38 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 39 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 40 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 41 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 42 VIRTIO_GPU_CMD_SUBMIT_3D, 43 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 44 VIRTIO_GPU_CMD_MOVE_CURSOR, 45 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 46 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 47 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 48 VIRTIO_GPU_RESP_OK_CAPSET, 49 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 50 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 51 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 52 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 53 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 54 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 55 }; 56 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 57 struct virtio_gpu_ctrl_hdr { 58 __le32 type; 59 __le32 flags; 60 __le64 fence_id; 61 __le32 ctx_id; 62 __le32 padding; 63 }; 64 struct virtio_gpu_cursor_pos { 65 __le32 scanout_id; 66 __le32 x; 67 __le32 y; 68 __le32 padding; 69 }; 70 struct virtio_gpu_update_cursor { 71 struct virtio_gpu_ctrl_hdr hdr; 72 struct virtio_gpu_cursor_pos pos; 73 __le32 resource_id; 74 __le32 hot_x; 75 __le32 hot_y; 76 __le32 padding; 77 }; 78 struct virtio_gpu_rect { 79 __le32 x; 80 __le32 y; 81 __le32 width; 82 __le32 height; 83 }; 84 struct virtio_gpu_resource_unref { 85 struct virtio_gpu_ctrl_hdr hdr; 86 __le32 resource_id; 87 __le32 padding; 88 }; 89 struct virtio_gpu_resource_create_2d { 90 struct virtio_gpu_ctrl_hdr hdr; 91 __le32 resource_id; 92 __le32 format; 93 __le32 width; 94 __le32 height; 95 }; 96 struct virtio_gpu_set_scanout { 97 struct virtio_gpu_ctrl_hdr hdr; 98 struct virtio_gpu_rect r; 99 __le32 scanout_id; 100 __le32 resource_id; 101 }; 102 struct virtio_gpu_resource_flush { 103 struct virtio_gpu_ctrl_hdr hdr; 104 struct virtio_gpu_rect r; 105 __le32 resource_id; 106 __le32 padding; 107 }; 108 struct virtio_gpu_transfer_to_host_2d { 109 struct virtio_gpu_ctrl_hdr hdr; 110 struct virtio_gpu_rect r; 111 __le64 offset; 112 __le32 resource_id; 113 __le32 padding; 114 }; 115 struct virtio_gpu_mem_entry { 116 __le64 addr; 117 __le32 length; 118 __le32 padding; 119 }; 120 struct virtio_gpu_resource_attach_backing { 121 struct virtio_gpu_ctrl_hdr hdr; 122 __le32 resource_id; 123 __le32 nr_entries; 124 }; 125 struct virtio_gpu_resource_detach_backing { 126 struct virtio_gpu_ctrl_hdr hdr; 127 __le32 resource_id; 128 __le32 padding; 129 }; 130 #define VIRTIO_GPU_MAX_SCANOUTS 16 131 struct virtio_gpu_resp_display_info { 132 struct virtio_gpu_ctrl_hdr hdr; 133 struct virtio_gpu_display_one { 134 struct virtio_gpu_rect r; 135 __le32 enabled; 136 __le32 flags; 137 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 138 }; 139 struct virtio_gpu_box { 140 __le32 x, y, z; 141 __le32 w, h, d; 142 }; 143 struct virtio_gpu_transfer_host_3d { 144 struct virtio_gpu_ctrl_hdr hdr; 145 struct virtio_gpu_box box; 146 __le64 offset; 147 __le32 resource_id; 148 __le32 level; 149 __le32 stride; 150 __le32 layer_stride; 151 }; 152 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 153 struct virtio_gpu_resource_create_3d { 154 struct virtio_gpu_ctrl_hdr hdr; 155 __le32 resource_id; 156 __le32 target; 157 __le32 format; 158 __le32 bind; 159 __le32 width; 160 __le32 height; 161 __le32 depth; 162 __le32 array_size; 163 __le32 last_level; 164 __le32 nr_samples; 165 __le32 flags; 166 __le32 padding; 167 }; 168 struct virtio_gpu_ctx_create { 169 struct virtio_gpu_ctrl_hdr hdr; 170 __le32 nlen; 171 __le32 padding; 172 char debug_name[64]; 173 }; 174 struct virtio_gpu_ctx_destroy { 175 struct virtio_gpu_ctrl_hdr hdr; 176 }; 177 struct virtio_gpu_ctx_resource { 178 struct virtio_gpu_ctrl_hdr hdr; 179 __le32 resource_id; 180 __le32 padding; 181 }; 182 struct virtio_gpu_cmd_submit { 183 struct virtio_gpu_ctrl_hdr hdr; 184 __le32 size; 185 __le32 padding; 186 }; 187 #define VIRTIO_GPU_CAPSET_VIRGL 1 188 struct virtio_gpu_get_capset_info { 189 struct virtio_gpu_ctrl_hdr hdr; 190 __le32 capset_index; 191 __le32 padding; 192 }; 193 struct virtio_gpu_resp_capset_info { 194 struct virtio_gpu_ctrl_hdr hdr; 195 __le32 capset_id; 196 __le32 capset_max_version; 197 __le32 capset_max_size; 198 __le32 padding; 199 }; 200 struct virtio_gpu_get_capset { 201 struct virtio_gpu_ctrl_hdr hdr; 202 __le32 capset_id; 203 __le32 capset_version; 204 }; 205 struct virtio_gpu_resp_capset { 206 struct virtio_gpu_ctrl_hdr hdr; 207 __u8 capset_data[]; 208 }; 209 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 210 struct virtio_gpu_config { 211 __u32 events_read; 212 __u32 events_clear; 213 __u32 num_scanouts; 214 __u32 num_capsets; 215 }; 216 enum virtio_gpu_formats { 217 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 218 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 219 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 220 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 221 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 222 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 223 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 224 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 225 }; 226 #endif 227
