1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #define MSM_PIPE_NONE 0x00 25 #define MSM_PIPE_2D0 0x01 26 #define MSM_PIPE_2D1 0x02 27 #define MSM_PIPE_3D0 0x10 28 #define MSM_PIPE_ID_MASK 0xffff 29 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 30 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 31 struct drm_msm_timespec { 32 __s64 tv_sec; 33 __s64 tv_nsec; 34 }; 35 #define MSM_PARAM_GPU_ID 0x01 36 #define MSM_PARAM_GMEM_SIZE 0x02 37 #define MSM_PARAM_CHIP_ID 0x03 38 #define MSM_PARAM_MAX_FREQ 0x04 39 #define MSM_PARAM_TIMESTAMP 0x05 40 struct drm_msm_param { 41 __u32 pipe; 42 __u32 param; 43 __u64 value; 44 }; 45 #define MSM_BO_SCANOUT 0x00000001 46 #define MSM_BO_GPU_READONLY 0x00000002 47 #define MSM_BO_CACHE_MASK 0x000f0000 48 #define MSM_BO_CACHED 0x00010000 49 #define MSM_BO_WC 0x00020000 50 #define MSM_BO_UNCACHED 0x00040000 51 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 52 struct drm_msm_gem_new { 53 __u64 size; 54 __u32 flags; 55 __u32 handle; 56 }; 57 struct drm_msm_gem_info { 58 __u32 handle; 59 __u32 pad; 60 __u64 offset; 61 }; 62 #define MSM_PREP_READ 0x01 63 #define MSM_PREP_WRITE 0x02 64 #define MSM_PREP_NOSYNC 0x04 65 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 66 struct drm_msm_gem_cpu_prep { 67 __u32 handle; 68 __u32 op; 69 struct drm_msm_timespec timeout; 70 }; 71 struct drm_msm_gem_cpu_fini { 72 __u32 handle; 73 }; 74 struct drm_msm_gem_submit_reloc { 75 __u32 submit_offset; 76 __u32 or; 77 __s32 shift; 78 __u32 reloc_idx; 79 __u64 reloc_offset; 80 }; 81 #define MSM_SUBMIT_CMD_BUF 0x0001 82 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 83 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 84 struct drm_msm_gem_submit_cmd { 85 __u32 type; 86 __u32 submit_idx; 87 __u32 submit_offset; 88 __u32 size; 89 __u32 pad; 90 __u32 nr_relocs; 91 __u64 __user relocs; 92 }; 93 #define MSM_SUBMIT_BO_READ 0x0001 94 #define MSM_SUBMIT_BO_WRITE 0x0002 95 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 96 struct drm_msm_gem_submit_bo { 97 __u32 flags; 98 __u32 handle; 99 __u64 presumed; 100 }; 101 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 102 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 103 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 104 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0) 105 struct drm_msm_gem_submit { 106 __u32 flags; 107 __u32 fence; 108 __u32 nr_bos; 109 __u32 nr_cmds; 110 __u64 __user bos; 111 __u64 __user cmds; 112 __s32 fence_fd; 113 }; 114 struct drm_msm_wait_fence { 115 __u32 fence; 116 __u32 pad; 117 struct drm_msm_timespec timeout; 118 }; 119 #define MSM_MADV_WILLNEED 0 120 #define MSM_MADV_DONTNEED 1 121 #define __MSM_MADV_PURGED 2 122 struct drm_msm_gem_madvise { 123 __u32 handle; 124 __u32 madv; 125 __u32 retained; 126 }; 127 #define DRM_MSM_GET_PARAM 0x00 128 #define DRM_MSM_GEM_NEW 0x02 129 #define DRM_MSM_GEM_INFO 0x03 130 #define DRM_MSM_GEM_CPU_PREP 0x04 131 #define DRM_MSM_GEM_CPU_FINI 0x05 132 #define DRM_MSM_GEM_SUBMIT 0x06 133 #define DRM_MSM_WAIT_FENCE 0x07 134 #define DRM_MSM_GEM_MADVISE 0x08 135 #define DRM_MSM_NUM_IOCTLS 0x09 136 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 137 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 138 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 139 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 140 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 141 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 142 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 143 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 144 #ifdef __cplusplus 145 #endif 146 #endif 147
