1 /* 2 * Copyright (C) 2017 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef __LOCAL_POC_H__ 17 #define __LOCAL_POC_H__ 18 19 #define SIOCIWFIRSTPRIV 0x8BE0 20 #define SIOCGIWNAME 0x8B01 21 #define IOCTL_SET_STRUCT_FOR_EM (SIOCIWFIRSTPRIV + 11) 22 #define PRIV_CUSTOM_BWCS_CMD 13 23 #define PRIV_CMD_OID 15 24 #define PRIV_CMD_SW_CTRL 20 25 #define PRIV_CMD_WSC_PROBE_REQ 22 26 27 enum host1x_class { 28 HOST1X_CLASS_HOST1X = 0x1, 29 HOST1X_CLASS_NVENC = 0x21, 30 HOST1X_CLASS_VI = 0x30, 31 HOST1X_CLASS_ISPA = 0x32, 32 HOST1X_CLASS_ISPB = 0x34, 33 HOST1X_CLASS_GR2D = 0x51, 34 HOST1X_CLASS_GR2D_SB = 0x52, 35 HOST1X_CLASS_VIC = 0x5D, 36 HOST1X_CLASS_GR3D = 0x60, 37 HOST1X_CLASS_NVJPG = 0xC0, 38 HOST1X_CLASS_NVDEC = 0xF0, 39 }; 40 41 #define DRM_TEGRA_GEM_CREATE 0x00 42 #define DRM_COMMAND_BASE 0x40 43 #define DRM_COMMAND_END 0xA0 44 45 #define DRM_TEGRA_OPEN_CHANNEL 0x05 46 #define DRM_TEGRA_CLOSE_CHANNEL 0x06 47 #define DRM_TEGRA_SUBMIT 0x08 48 49 struct drm_tegra_open_channel { 50 __u32 client; 51 __u32 pad; 52 __u64 context; 53 }; 54 55 struct drm_tegra_close_channel { 56 __u64 context; 57 }; 58 59 struct drm_tegra_cmdbuf { 60 __u32 handle; 61 __u32 offset; 62 __u32 words; 63 __u32 pad; 64 }; 65 66 struct host1x_waitchk { 67 struct host1x_bo *bo; 68 __u32 offset; 69 __u32 syncpt_id; 70 __u32 thresh; 71 }; 72 73 struct drm_tegra_waitchk { 74 __u32 handle; 75 __u32 offset; 76 __u32 syncpt; 77 __u32 thresh; 78 }; 79 80 struct drm_tegra_submit { 81 __u64 context; 82 __u32 num_syncpts; 83 __u32 num_cmdbufs; 84 __u32 num_relocs; 85 __u32 num_waitchks; 86 __u32 waitchk_mask; 87 __u32 timeout; 88 __u64 syncpts; 89 __u64 cmdbufs; 90 __u64 relocs; 91 __u64 waitchks; 92 __u32 fence; /* Return value */ 93 __u32 reserved0; 94 __u64 fences; 95 __u32 reserved1[2]; /* future expansion */ 96 }; 97 98 struct drm_tegra_gem_create { 99 __u64 size; 100 __u32 flags; 101 __u32 handle; 102 }; 103 104 struct drm_gem_close { 105 __u32 handle; 106 __u32 pad; 107 }; 108 109 struct drm_mode_map_dumb { 110 __u32 handle; 111 __u32 pad; 112 __u64 offset; 113 }; 114 115 #define DRM_IOCTL_BASE 'd' 116 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 117 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 118 119 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) 120 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel) 121 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) 122 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) 123 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 124 #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 125 126 struct drm_tegra_syncpt { 127 __u32 id; 128 __u32 incrs; 129 }; 130 131 struct list_head { 132 struct list_head *next, *prev; 133 }; 134 135 struct kobject { 136 const char *name; 137 struct list_head entry; 138 struct kobject *parent; 139 void *kset; 140 void *ktype; 141 void *sd; 142 unsigned long refcount; 143 unsigned int state_initialized:1; 144 unsigned int state_in_sysfs:1; 145 unsigned int state_add_uevent_sent:1; 146 unsigned int state_remove_uevent_sent:1; 147 unsigned int uevent_suppress:1; 148 }; 149 150 struct device { 151 struct device *parent; 152 void *p; 153 void* pad0[8]; 154 char *init_name; 155 void *type; 156 void* pad1[5]; 157 void *bus; 158 void *driver; 159 void *platform_data; 160 void *driver_data; 161 }; 162 163 struct host1x_info { 164 int nb_channels; 165 int nb_pts; 166 int nb_bases; 167 int nb_mlocks; 168 int (*init)(void *); 169 int sync_offset; 170 }; 171 172 struct host1x_syncpt_ops { 173 void (*restore)(void *syncpt); 174 void (*restore_wait_base)(void *syncpt); 175 void (*load_wait_base)(void *syncpt); 176 __u32 (*load)(void *syncpt); 177 int (*cpu_incr)(void *syncpt); 178 int (*patch_wait)(void *syncpt, void *patch_addr); 179 }; 180 181 struct host1x { 182 struct host1x_info *info; 183 void *regs; 184 void *syncpt; 185 void *bases; 186 struct device *dev; 187 void *clk; 188 void *clk_actmon; 189 void* pad[5]; 190 void *intr_wq; 191 int intr_syncpt_irq; 192 int intr_general_irq; 193 __u32 intstatus; 194 void (*host_isr[32])(__u32, void *); 195 void *host_isr_priv[32]; 196 struct host1x_syncpt_ops *syncpt_op; 197 void *intr_op; 198 void *channel_op; 199 void *cdma_op; 200 void *cdma_pb_op; 201 void *actmon_op; 202 void *debug_op; 203 }; 204 205 struct host1x_client { 206 struct list_head list; 207 void *parent; 208 struct device *dev; 209 void *ops; 210 }; 211 212 struct tegra_drm_client_ops { 213 void* open_channel; 214 void* close_channel; 215 void* reset; 216 void* is_add_reg; 217 void* submit; 218 }; 219 220 struct tegra_drm_client { 221 unsigned char pad[232]; 222 struct list_head list; 223 struct tegra_drm_client_ops *ops; 224 }; 225 226 struct tegra_drm_context { 227 struct tegra_drm_client *client; 228 void *channel; 229 struct list_head list; 230 }; 231 232 struct drm_tegra_reloc { 233 struct { 234 __u32 handle; 235 __u32 offset; 236 } cmdbuf; 237 struct { 238 __u32 handle; 239 __u32 offset; 240 } target; 241 __u32 shift; 242 __u32 pad; 243 }; 244 245 #endif 246
