1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <platform.h> 36 #include <platform_def.h> 37 #include <string.h> 38 #include "fvp_def.h" 39 #include "fvp_private.h" 40 41 /******************************************************************************* 42 * Declarations of linker defined symbols which will help us find the layout 43 * of trusted SRAM 44 ******************************************************************************/ 45 extern unsigned long __RO_START__; 46 extern unsigned long __RO_END__; 47 48 #if USE_COHERENT_MEM 49 extern unsigned long __COHERENT_RAM_START__; 50 extern unsigned long __COHERENT_RAM_END__; 51 #endif 52 53 /* 54 * The next 2 constants identify the extents of the code & RO data region. 55 * These addresses are used by the MMU setup code and therefore they must be 56 * page-aligned. It is the responsibility of the linker script to ensure that 57 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 58 */ 59 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 60 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 61 62 #if USE_COHERENT_MEM 63 /* 64 * The next 2 constants identify the extents of the coherent memory region. 65 * These addresses are used by the MMU setup code and therefore they must be 66 * page-aligned. It is the responsibility of the linker script to ensure that 67 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 68 * page-aligned addresses. 69 */ 70 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 71 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 72 #endif 73 74 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 75 static meminfo_t bl2_tzram_layout 76 __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE))); 77 78 /* Assert that BL3-1 parameters fit in shared memory */ 79 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) < 80 (FVP_SHARED_MEM_BASE + FVP_SHARED_MEM_SIZE), 81 assert_bl31_params_do_not_fit_in_shared_memory); 82 83 /******************************************************************************* 84 * Reference to structures which holds the arguments which need to be passed 85 * to BL31 86 ******************************************************************************/ 87 static bl31_params_t *bl2_to_bl31_params; 88 static entry_point_info_t *bl31_ep_info; 89 90 meminfo_t *bl2_plat_sec_mem_layout(void) 91 { 92 return &bl2_tzram_layout; 93 } 94 95 /******************************************************************************* 96 * This function assigns a pointer to the memory that the platform has kept 97 * aside to pass platform specific and trusted firmware related information 98 * to BL31. This memory is allocated by allocating memory to 99 * bl2_to_bl31_params_mem_t structure which is a superset of all the 100 * structure whose information is passed to BL31 101 * NOTE: This function should be called only once and should be done 102 * before generating params to BL31 103 ******************************************************************************/ 104 bl31_params_t *bl2_plat_get_bl31_params(void) 105 { 106 bl2_to_bl31_params_mem_t *bl31_params_mem; 107 108 /* 109 * Allocate the memory for all the arguments that needs to 110 * be passed to BL31 111 */ 112 bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 113 memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t)); 114 115 /* Assign memory for TF related information */ 116 bl2_to_bl31_params = &bl31_params_mem->bl31_params; 117 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 118 119 /* Fill BL31 related information */ 120 bl31_ep_info = &bl31_params_mem->bl31_ep_info; 121 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info; 122 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 123 VERSION_1, 0); 124 125 /* Fill BL32 related information if it exists */ 126 if (BL32_BASE) { 127 bl2_to_bl31_params->bl32_ep_info = 128 &bl31_params_mem->bl32_ep_info; 129 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, 130 PARAM_EP, VERSION_1, 0); 131 bl2_to_bl31_params->bl32_image_info = 132 &bl31_params_mem->bl32_image_info; 133 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, 134 PARAM_IMAGE_BINARY, 135 VERSION_1, 0); 136 } 137 138 /* Fill BL33 related information */ 139 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info; 140 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 141 PARAM_EP, VERSION_1, 0); 142 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info; 143 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 144 VERSION_1, 0); 145 146 return bl2_to_bl31_params; 147 } 148 149 150 /******************************************************************************* 151 * This function returns a pointer to the shared memory that the platform 152 * has kept to point to entry point information of BL31 to BL2 153 ******************************************************************************/ 154 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 155 { 156 #if DEBUG 157 bl31_ep_info->args.arg1 = FVP_BL31_PLAT_PARAM_VAL; 158 #endif 159 return bl31_ep_info; 160 } 161 162 163 /******************************************************************************* 164 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 165 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 166 * Copy it to a safe loaction before its reclaimed by later BL2 functionality. 167 ******************************************************************************/ 168 void bl2_early_platform_setup(meminfo_t *mem_layout) 169 { 170 /* Initialize the console to provide early debug support */ 171 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 172 173 /* Setup the BL2 memory layout */ 174 bl2_tzram_layout = *mem_layout; 175 176 /* Initialize the platform config for future decision making */ 177 fvp_config_setup(); 178 179 /* Initialise the IO layer and register platform IO devices */ 180 fvp_io_setup(); 181 } 182 183 /******************************************************************************* 184 * Perform platform specific setup. For now just initialize the memory location 185 * to use for passing arguments to BL31. 186 ******************************************************************************/ 187 void bl2_platform_setup(void) 188 { 189 /* 190 * Do initial security configuration to allow DRAM/device access. On 191 * Base FVP only DRAM security is programmable (via TrustZone), but 192 * other platforms might have more programmable security devices 193 * present. 194 */ 195 fvp_security_setup(); 196 } 197 198 /* Flush the TF params and the TF plat params */ 199 void bl2_plat_flush_bl31_params(void) 200 { 201 flush_dcache_range((unsigned long)PARAMS_BASE, \ 202 sizeof(bl2_to_bl31_params_mem_t)); 203 } 204 205 206 /******************************************************************************* 207 * Perform the very early platform specific architectural setup here. At the 208 * moment this is only intializes the mmu in a quick and dirty way. 209 ******************************************************************************/ 210 void bl2_plat_arch_setup(void) 211 { 212 fvp_configure_mmu_el1(bl2_tzram_layout.total_base, 213 bl2_tzram_layout.total_size, 214 BL2_RO_BASE, 215 BL2_RO_LIMIT 216 #if USE_COHERENT_MEM 217 , BL2_COHERENT_RAM_BASE, 218 BL2_COHERENT_RAM_LIMIT 219 #endif 220 ); 221 } 222 223 /******************************************************************************* 224 * Before calling this function BL31 is loaded in memory and its entrypoint 225 * is set by load_image. This is a placeholder for the platform to change 226 * the entrypoint of BL31 and set SPSR and security state. 227 * On FVP we are only setting the security state, entrypoint 228 ******************************************************************************/ 229 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 230 entry_point_info_t *bl31_ep_info) 231 { 232 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 233 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 234 DISABLE_ALL_EXCEPTIONS); 235 } 236 237 238 /******************************************************************************* 239 * Before calling this function BL32 is loaded in memory and its entrypoint 240 * is set by load_image. This is a placeholder for the platform to change 241 * the entrypoint of BL32 and set SPSR and security state. 242 * On FVP we are only setting the security state, entrypoint 243 ******************************************************************************/ 244 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 245 entry_point_info_t *bl32_ep_info) 246 { 247 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 248 bl32_ep_info->spsr = fvp_get_spsr_for_bl32_entry(); 249 } 250 251 /******************************************************************************* 252 * Before calling this function BL33 is loaded in memory and its entrypoint 253 * is set by load_image. This is a placeholder for the platform to change 254 * the entrypoint of BL33 and set SPSR and security state. 255 * On FVP we are only setting the security state, entrypoint 256 ******************************************************************************/ 257 void bl2_plat_set_bl33_ep_info(image_info_t *image, 258 entry_point_info_t *bl33_ep_info) 259 { 260 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 261 bl33_ep_info->spsr = fvp_get_spsr_for_bl33_entry(); 262 } 263 264 265 /******************************************************************************* 266 * Populate the extents of memory available for loading BL32 267 ******************************************************************************/ 268 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 269 { 270 /* 271 * Populate the extents of memory available for loading BL32. 272 */ 273 bl32_meminfo->total_base = BL32_BASE; 274 bl32_meminfo->free_base = BL32_BASE; 275 bl32_meminfo->total_size = 276 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 277 bl32_meminfo->free_size = 278 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 279 } 280 281 282 /******************************************************************************* 283 * Populate the extents of memory available for loading BL33 284 ******************************************************************************/ 285 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 286 { 287 bl33_meminfo->total_base = DRAM1_NS_BASE; 288 bl33_meminfo->total_size = DRAM1_NS_SIZE; 289 bl33_meminfo->free_base = DRAM1_NS_BASE; 290 bl33_meminfo->free_size = DRAM1_NS_SIZE; 291 } 292
