1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /******************************************************************************* 33 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a 34 * plug-in component to the Secure Monitor, registered as a runtime service. The 35 * SPD is expected to be a functional extension of the Secure Payload (SP) that 36 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting 37 * the Trusted OS/Applications range to the dispatcher. The SPD will either 38 * handle the request locally or delegate it to the Secure Payload. It is also 39 * responsible for initialising and maintaining communication with the SP. 40 ******************************************************************************/ 41 #include <arch_helpers.h> 42 #include <assert.h> 43 #include <bl_common.h> 44 #include <bl31.h> 45 #include <context_mgmt.h> 46 #include <debug.h> 47 #include <errno.h> 48 #include <platform.h> 49 #include <runtime_svc.h> 50 #include <stddef.h> 51 #include <string.h> 52 #include <uuid.h> 53 #include "opteed_private.h" 54 #include "teesmc_opteed_macros.h" 55 #include "teesmc_opteed.h" 56 57 #define OPTEE_MAGIC 0x4554504f 58 #define OPTEE_VERSION 1 59 #define OPTEE_ARCH_ARM32 0 60 #define OPTEE_ARCH_ARM64 1 61 62 struct optee_header { 63 uint32_t magic; 64 uint8_t version; 65 uint8_t arch; 66 uint16_t flags; 67 uint32_t init_size; 68 uint32_t init_load_addr_hi; 69 uint32_t init_load_addr_lo; 70 uint32_t init_mem_usage; 71 uint32_t paged_size; 72 }; 73 74 /******************************************************************************* 75 * Address of the entrypoint vector table in OPTEE. It is 76 * initialised once on the primary core after a cold boot. 77 ******************************************************************************/ 78 optee_vectors_t *optee_vectors; 79 80 /******************************************************************************* 81 * Array to keep track of per-cpu OPTEE state 82 ******************************************************************************/ 83 optee_context_t opteed_sp_context[OPTEED_CORE_COUNT]; 84 uint32_t opteed_rw; 85 86 87 88 static int32_t opteed_init(void); 89 90 /******************************************************************************* 91 * This function is the handler registered for S-EL1 interrupts by the 92 * OPTEED. It validates the interrupt and upon success arranges entry into 93 * the OPTEE at 'optee_fiq_entry()' for handling the interrupt. 94 ******************************************************************************/ 95 static uint64_t opteed_sel1_interrupt_handler(uint32_t id, 96 uint32_t flags, 97 void *handle, 98 void *cookie) 99 { 100 uint32_t linear_id; 101 uint64_t mpidr; 102 optee_context_t *optee_ctx; 103 104 /* Check the security state when the exception was generated */ 105 assert(get_interrupt_src_ss(flags) == NON_SECURE); 106 107 #if IMF_READ_INTERRUPT_ID 108 /* Check the security status of the interrupt */ 109 assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1); 110 #endif 111 112 /* Sanity check the pointer to this cpu's context */ 113 mpidr = read_mpidr(); 114 assert(handle == cm_get_context(NON_SECURE)); 115 116 /* Save the non-secure context before entering the OPTEE */ 117 cm_el1_sysregs_context_save(NON_SECURE); 118 119 /* Get a reference to this cpu's OPTEE context */ 120 linear_id = platform_get_core_pos(mpidr); 121 optee_ctx = &opteed_sp_context[linear_id]; 122 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); 123 124 cm_set_elr_el3(SECURE, (uint64_t)&optee_vectors->fiq_entry); 125 cm_el1_sysregs_context_restore(SECURE); 126 cm_set_next_eret_context(SECURE); 127 128 /* 129 * Tell the OPTEE that it has to handle an FIQ (synchronously). 130 * Also the instruction in normal world where the interrupt was 131 * generated is passed for debugging purposes. It is safe to 132 * retrieve this address from ELR_EL3 as the secure context will 133 * not take effect until el3_exit(). 134 */ 135 SMC_RET1(&optee_ctx->cpu_ctx, read_elr_el3()); 136 } 137 138 139 static int is_mem_free(uint64_t free_base, size_t free_size, 140 uint64_t addr, size_t size) 141 { 142 return (addr >= free_base) && (addr + size <= free_base + free_size); 143 } 144 145 /******************************************************************************* 146 * OPTEE Dispatcher setup. The OPTEED finds out the OPTEE entrypoint and type 147 * (aarch32/aarch64) if not already known and initialises the context for entry 148 * into OPTEE for its initialization. 149 ******************************************************************************/ 150 int32_t opteed_setup(void) 151 { 152 entry_point_info_t *ep_info; 153 struct optee_header *header; 154 uint64_t mpidr = read_mpidr(); 155 uint32_t linear_id; 156 uintptr_t init_load_addr; 157 size_t init_size; 158 size_t init_mem_usage; 159 uintptr_t payload_addr; 160 uintptr_t mem_limit; 161 uintptr_t paged_part; 162 uintptr_t paged_size; 163 164 linear_id = platform_get_core_pos(mpidr); 165 166 /* 167 * Get information about the Secure Payload (BL32) image. Its 168 * absence is a critical failure. TODO: Add support to 169 * conditionally include the SPD service 170 */ 171 ep_info = bl31_plat_get_next_image_ep_info(SECURE); 172 if (!ep_info) { 173 WARN("No OPTEE provided by BL2 boot loader.\n"); 174 goto err; 175 } 176 177 header = (struct optee_header *)ep_info->pc; 178 179 if (header->magic != OPTEE_MAGIC || header->version != OPTEE_VERSION) { 180 WARN("Invalid OPTEE header.\n"); 181 goto err; 182 } 183 184 if (header->arch == OPTEE_ARCH_ARM32) 185 opteed_rw = OPTEE_AARCH32; 186 else if (header->arch == OPTEE_ARCH_ARM64) 187 opteed_rw = OPTEE_AARCH64; 188 else { 189 WARN("Invalid OPTEE architecture (%d)\n", header->arch); 190 goto err; 191 } 192 193 init_load_addr = ((uint64_t)header->init_load_addr_hi << 32) | 194 header->init_load_addr_lo; 195 init_size = header->init_size; 196 init_mem_usage = header->init_mem_usage; 197 payload_addr = (uintptr_t)(header + 1); 198 paged_size = header->paged_size; 199 200 /* 201 * Move OPTEE binary to the required location in memory. 202 * 203 * There's two ways OPTEE can be running in memory: 204 * 1. A memory large enough to keep the entire OPTEE binary 205 * (DRAM currently) 206 * 2. A part of OPTEE in a smaller (and more secure) memory 207 * (SRAM currently). This is achieved with demand paging 208 * of read-only data/code against a backing store in some 209 * larger memory (DRAM currently). 210 * 211 * In either case dictates init_load_addr in the OPTEE 212 * header the address where what's after the header 213 * (payload) should be residing when started. init_size in 214 * the header tells how much of the payload that need to be 215 * copied. init_mem_usage tells how much runtime memory in 216 * total is needed by OPTEE. 217 * 218 * In alternative 2 there's additional data after 219 * init_size, this is the rest of OPTEE which is demand 220 * paged into memory. A pointer to that data is supplied 221 * to OPTEE when initializing. 222 * 223 * Alternative 1 only uses DRAM when executing OPTEE while 224 * alternative 2 uses both SRAM and DRAM to execute. 225 * 226 * All data written which is later read by OPTEE must be flushed 227 * out to memory since OPTEE starts with MMU turned off and caches 228 * disabled. 229 */ 230 if (is_mem_free(BL32_SRAM_BASE, 231 BL32_SRAM_LIMIT - BL32_SRAM_BASE, 232 init_load_addr, init_mem_usage)) { 233 /* Running in SRAM, paging some code against DRAM */ 234 memcpy((void *)init_load_addr, (void *)payload_addr, 235 init_size); 236 flush_dcache_range(init_load_addr, init_size); 237 paged_part = payload_addr + init_size; 238 mem_limit = BL32_SRAM_LIMIT; 239 } else if (is_mem_free(BL32_DRAM_BASE, 240 BL32_DRAM_LIMIT - BL32_DRAM_BASE, 241 init_load_addr, init_mem_usage)) { 242 /* 243 * Running in DRAM. 244 * 245 * The paged part normally empty, but if it isn't, 246 * move it to the end of DRAM before moving the 247 * init part in place. 248 */ 249 paged_part = BL32_DRAM_LIMIT - paged_size; 250 if (paged_size) { 251 if (!is_mem_free(BL32_DRAM_BASE, 252 BL32_DRAM_LIMIT - BL32_DRAM_BASE, 253 init_load_addr, 254 init_mem_usage + paged_size)) { 255 WARN("Failed to reserve memory 0x%lx - 0x%lx\n", 256 init_load_addr, 257 init_load_addr + init_mem_usage + 258 paged_size); 259 goto err; 260 } 261 262 memcpy((void *)paged_part, 263 (void *)(payload_addr + init_size), 264 paged_size); 265 flush_dcache_range(paged_part, paged_size); 266 } 267 268 memmove((void *)init_load_addr, (void *)payload_addr, 269 init_size); 270 flush_dcache_range(init_load_addr, init_size); 271 mem_limit = BL32_DRAM_LIMIT; 272 } else { 273 WARN("Failed to reserve memory 0x%lx - 0x%lx\n", 274 init_load_addr, init_load_addr + init_mem_usage); 275 goto err; 276 } 277 278 279 opteed_init_optee_ep_state(ep_info, opteed_rw, init_load_addr, 280 paged_part, mem_limit, 281 &opteed_sp_context[linear_id]); 282 283 /* 284 * All OPTEED initialization done. Now register our init function with 285 * BL31 for deferred invocation 286 */ 287 bl31_register_bl32_init(&opteed_init); 288 289 return 0; 290 291 err: 292 WARN("Booting device without OPTEE initialization.\n"); 293 WARN("SMC`s destined for OPTEE will return SMC_UNK\n"); 294 return 1; 295 } 296 297 /******************************************************************************* 298 * This function passes control to the OPTEE image (BL32) for the first time 299 * on the primary cpu after a cold boot. It assumes that a valid secure 300 * context has already been created by opteed_setup() which can be directly 301 * used. It also assumes that a valid non-secure context has been 302 * initialised by PSCI so it does not need to save and restore any 303 * non-secure state. This function performs a synchronous entry into 304 * OPTEE. OPTEE passes control back to this routine through a SMC. 305 ******************************************************************************/ 306 static int32_t opteed_init(void) 307 { 308 uint64_t mpidr = read_mpidr(); 309 uint32_t linear_id = platform_get_core_pos(mpidr); 310 optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; 311 entry_point_info_t *optee_entry_point; 312 uint64_t rc; 313 314 /* 315 * Get information about the OPTEE (BL32) image. Its 316 * absence is a critical failure. 317 */ 318 optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE); 319 assert(optee_entry_point); 320 321 cm_init_context(mpidr, optee_entry_point); 322 323 /* 324 * Arrange for an entry into OPTEE. It will be returned via 325 * OPTEE_ENTRY_DONE case 326 */ 327 rc = opteed_synchronous_sp_entry(optee_ctx); 328 assert(rc != 0); 329 330 return rc; 331 } 332 333 334 /******************************************************************************* 335 * This function is responsible for handling all SMCs in the Trusted OS/App 336 * range from the non-secure state as defined in the SMC Calling Convention 337 * Document. It is also responsible for communicating with the Secure 338 * payload to delegate work and return results back to the non-secure 339 * state. Lastly it will also return any information that OPTEE needs to do 340 * the work assigned to it. 341 ******************************************************************************/ 342 uint64_t opteed_smc_handler(uint32_t smc_fid, 343 uint64_t x1, 344 uint64_t x2, 345 uint64_t x3, 346 uint64_t x4, 347 void *cookie, 348 void *handle, 349 uint64_t flags) 350 { 351 cpu_context_t *ns_cpu_context; 352 unsigned long mpidr = read_mpidr(); 353 uint32_t linear_id = platform_get_core_pos(mpidr); 354 optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; 355 uint64_t rc; 356 357 /* 358 * Determine which security state this SMC originated from 359 */ 360 361 if (is_caller_non_secure(flags)) { 362 gp_regs_t *sec_gpregs = get_gpregs_ctx(&optee_ctx->cpu_ctx); 363 gp_regs_t *ns_gpregs = get_gpregs_ctx(handle); 364 365 /* 366 * This is a fresh request from the non-secure client. 367 * The parameters are in x1 and x2. Figure out which 368 * registers need to be preserved, save the non-secure 369 * state and send the request to the secure payload. 370 */ 371 assert(handle == cm_get_context(NON_SECURE)); 372 373 cm_el1_sysregs_context_save(NON_SECURE); 374 375 /* 376 * We are done stashing the non-secure context. Ask the 377 * OPTEE to do the work now. 378 */ 379 380 /* 381 * Verify if there is a valid context to use, copy the 382 * operation type and parameters to the secure context 383 * and jump to the fast smc entry point in the secure 384 * payload. Entry into S-EL1 will take place upon exit 385 * from this function. 386 */ 387 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); 388 389 /* Set appropriate entry for SMC. 390 * We expect OPTEE to manage the PSTATE.I and PSTATE.F 391 * flags as appropriate. 392 */ 393 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { 394 cm_set_elr_el3(SECURE, (uint64_t) 395 &optee_vectors->fast_smc_entry); 396 } else { 397 cm_set_elr_el3(SECURE, (uint64_t) 398 &optee_vectors->std_smc_entry); 399 } 400 401 cm_el1_sysregs_context_restore(SECURE); 402 cm_set_next_eret_context(SECURE); 403 404 /* Propagate X4-X7 */ 405 write_ctx_reg(sec_gpregs, CTX_GPREG_X4, 406 read_ctx_reg(ns_gpregs, CTX_GPREG_X4)); 407 write_ctx_reg(sec_gpregs, CTX_GPREG_X5, 408 read_ctx_reg(ns_gpregs, CTX_GPREG_X5)); 409 write_ctx_reg(sec_gpregs, CTX_GPREG_X6, 410 read_ctx_reg(ns_gpregs, CTX_GPREG_X6)); 411 write_ctx_reg(sec_gpregs, CTX_GPREG_X7, 412 read_ctx_reg(ns_gpregs, CTX_GPREG_X7)); 413 414 SMC_RET4(&optee_ctx->cpu_ctx, smc_fid, x1, x2, x3); 415 } 416 417 /* 418 * Returning from OPTEE 419 */ 420 421 switch (smc_fid) { 422 /* 423 * OPTEE has finished initialising itself after a cold boot 424 */ 425 case TEESMC_OPTEED_RETURN_ENTRY_DONE: 426 /* 427 * Stash the OPTEE entry points information. This is done 428 * only once on the primary cpu 429 */ 430 assert(optee_vectors == NULL); 431 optee_vectors = (optee_vectors_t *) x1; 432 433 if (optee_vectors) { 434 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); 435 436 /* 437 * OPTEE has been successfully initialized. 438 * Register power management hooks with PSCI 439 */ 440 psci_register_spd_pm_hook(&opteed_pm); 441 442 /* 443 * Register an interrupt handler for S-EL1 interrupts 444 * when generated during code executing in the 445 * non-secure state. 446 */ 447 flags = 0; 448 set_interrupt_rm_flag(flags, NON_SECURE); 449 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 450 opteed_sel1_interrupt_handler, 451 flags); 452 if (rc) 453 panic(); 454 } 455 456 /* 457 * OPTEE reports completion. The OPTEED must have initiated 458 * the original request through a synchronous entry into 459 * OPTEE. Jump back to the original C runtime context. 460 */ 461 opteed_synchronous_sp_exit(optee_ctx, x1); 462 463 464 /* 465 * These function IDs is used only by OP-TEE to indicate it has 466 * finished: 467 * 1. turning itself on in response to an earlier psci 468 * cpu_on request 469 * 2. resuming itself after an earlier psci cpu_suspend 470 * request. 471 */ 472 case TEESMC_OPTEED_RETURN_ON_DONE: 473 case TEESMC_OPTEED_RETURN_RESUME_DONE: 474 475 476 /* 477 * These function IDs is used only by the SP to indicate it has 478 * finished: 479 * 1. suspending itself after an earlier psci cpu_suspend 480 * request. 481 * 2. turning itself off in response to an earlier psci 482 * cpu_off request. 483 */ 484 case TEESMC_OPTEED_RETURN_OFF_DONE: 485 case TEESMC_OPTEED_RETURN_SUSPEND_DONE: 486 case TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE: 487 case TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE: 488 489 /* 490 * OPTEE reports completion. The OPTEED must have initiated the 491 * original request through a synchronous entry into OPTEE. 492 * Jump back to the original C runtime context, and pass x1 as 493 * return value to the caller 494 */ 495 opteed_synchronous_sp_exit(optee_ctx, x1); 496 497 /* 498 * OPTEE is returning from a call or being preempted from a call, in 499 * either case execution should resume in the normal world. 500 */ 501 case TEESMC_OPTEED_RETURN_CALL_DONE: 502 /* 503 * This is the result from the secure client of an 504 * earlier request. The results are in x0-x3. Copy it 505 * into the non-secure context, save the secure state 506 * and return to the non-secure state. 507 */ 508 assert(handle == cm_get_context(SECURE)); 509 cm_el1_sysregs_context_save(SECURE); 510 511 /* Get a reference to the non-secure context */ 512 ns_cpu_context = cm_get_context(NON_SECURE); 513 assert(ns_cpu_context); 514 515 /* Restore non-secure state */ 516 cm_el1_sysregs_context_restore(NON_SECURE); 517 cm_set_next_eret_context(NON_SECURE); 518 519 SMC_RET4(ns_cpu_context, x1, x2, x3, x4); 520 521 /* 522 * OPTEE has finished handling a S-EL1 FIQ interrupt. Execution 523 * should resume in the normal world. 524 */ 525 case TEESMC_OPTEED_RETURN_FIQ_DONE: 526 /* Get a reference to the non-secure context */ 527 ns_cpu_context = cm_get_context(NON_SECURE); 528 assert(ns_cpu_context); 529 530 /* 531 * Restore non-secure state. There is no need to save the 532 * secure system register context since OPTEE was supposed 533 * to preserve it during S-EL1 interrupt handling. 534 */ 535 cm_el1_sysregs_context_restore(NON_SECURE); 536 cm_set_next_eret_context(NON_SECURE); 537 538 SMC_RET0((uint64_t) ns_cpu_context); 539 540 default: 541 panic(); 542 } 543 } 544 545 /* Define an OPTEED runtime service descriptor for fast SMC calls */ 546 DECLARE_RT_SVC( 547 opteed_fast, 548 549 OEN_TOS_START, 550 OEN_TOS_END, 551 SMC_TYPE_FAST, 552 opteed_setup, 553 opteed_smc_handler 554 ); 555 556 /* Define an OPTEED runtime service descriptor for standard SMC calls */ 557 DECLARE_RT_SVC( 558 opteed_std, 559 560 OEN_TOS_START, 561 OEN_TOS_END, 562 SMC_TYPE_STD, 563 NULL, 564 opteed_smc_handler 565 ); 566
