1 /** @file 2 3 Copyright (c) 2011-2014, ARM Limited. All rights reserved. 4 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #include <Base.h> 16 #include <Library/ArmLib.h> 17 #include <Library/ArmCpuLib.h> 18 #include <Library/ArmGenericTimerCounterLib.h> 19 #include <Library/DebugLib.h> 20 #include <Library/PcdLib.h> 21 22 #include <Chipset/ArmCortexA5x.h> 23 24 VOID 25 ArmCpuSetup ( 26 IN UINTN MpId 27 ) 28 { 29 // Check if Architectural Timer frequency is valid number (should not be 0) 30 ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz)); 31 ASSERT (ArmIsArchTimerImplemented () != 0); 32 33 // Note: System Counter frequency can only be set in Secure privileged mode, 34 // if security extensions are implemented. 35 ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz)); 36 37 if (ArmIsMpCore ()) { 38 // Turn on SMP coherency 39 ArmSetCpuExCrBit (A5X_FEATURE_SMP); 40 } 41 42 // 43 // If CPU is CortexA57 r0p0 apply Errata: 806969 44 // 45 if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) == 46 ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) { 47 // DisableLoadStoreWB 48 ArmSetCpuActlrBit (1ULL << 49); 49 } 50 } 51 52 VOID 53 ArmCpuSetupSmpNonSecure ( 54 IN UINTN MpId 55 ) 56 { 57 } 58 59 VOID 60 EFIAPI 61 ArmSetCpuExCrBit ( 62 IN UINT64 Bits 63 ) 64 { 65 UINT64 Value; 66 Value = ArmReadCpuExCr (); 67 Value |= Bits; 68 ArmWriteCpuExCr (Value); 69 } 70 71 VOID 72 EFIAPI 73 ArmUnsetCpuExCrBit ( 74 IN UINT64 Bits 75 ) 76 { 77 UINT64 Value; 78 Value = ArmReadCpuExCr (); 79 Value &= ~Bits; 80 ArmWriteCpuExCr (Value); 81 } 82
