1 //------------------------------------------------------------------------------ 2 // 3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. 5 // 6 // This program and the accompanying materials 7 // are licensed and made available under the terms and conditions of the BSD License 8 // which accompanies this distribution. The full text of the license may be found at 9 // http://opensource.org/licenses/bsd-license.php 10 // 11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 // 14 //------------------------------------------------------------------------------ 15 16 #include <AsmMacroIoLib.h> 17 18 INCLUDE AsmMacroIoLib.inc 19 20 21 INCLUDE AsmMacroExport.inc 22 23 RVCT_ASM_EXPORT ArmReadMidr 24 mrc p15,0,R0,c0,c0,0 25 bx LR 26 27 RVCT_ASM_EXPORT ArmCacheInfo 28 mrc p15,0,R0,c0,c0,1 29 bx LR 30 31 RVCT_ASM_EXPORT ArmGetInterruptState 32 mrs R0,CPSR 33 tst R0,#0x80 // Check if IRQ is enabled. 34 moveq R0,#1 35 movne R0,#0 36 bx LR 37 38 RVCT_ASM_EXPORT ArmGetFiqState 39 mrs R0,CPSR 40 tst R0,#0x40 // Check if FIQ is enabled. 41 moveq R0,#1 42 movne R0,#0 43 bx LR 44 45 RVCT_ASM_EXPORT ArmSetDomainAccessControl 46 mcr p15,0,r0,c3,c0,0 47 bx lr 48 49 RVCT_ASM_EXPORT CPSRMaskInsert 50 stmfd sp!, {r4-r12, lr} // save all the banked registers 51 mov r3, sp // copy the stack pointer into a non-banked register 52 mrs r2, cpsr // read the cpsr 53 bic r2, r2, r0 // clear mask in the cpsr 54 and r1, r1, r0 // clear bits outside the mask in the input 55 orr r2, r2, r1 // set field 56 msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch) 57 isb 58 mov sp, r3 // restore stack pointer 59 ldmfd sp!, {r4-r12, lr} // restore registers 60 bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!) 61 62 RVCT_ASM_EXPORT CPSRRead 63 mrs r0, cpsr 64 bx lr 65 66 RVCT_ASM_EXPORT ArmReadCpacr 67 mrc p15, 0, r0, c1, c0, 2 68 bx lr 69 70 RVCT_ASM_EXPORT ArmWriteCpacr 71 mcr p15, 0, r0, c1, c0, 2 72 isb 73 bx lr 74 75 RVCT_ASM_EXPORT ArmWriteAuxCr 76 mcr p15, 0, r0, c1, c0, 1 77 bx lr 78 79 RVCT_ASM_EXPORT ArmReadAuxCr 80 mrc p15, 0, r0, c1, c0, 1 81 bx lr 82 83 RVCT_ASM_EXPORT ArmSetTTBR0 84 mcr p15,0,r0,c2,c0,0 85 isb 86 bx lr 87 88 RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress 89 mrc p15,0,r0,c2,c0,0 90 LoadConstantToReg(0xFFFFC000, r1) 91 and r0, r0, r1 92 isb 93 bx lr 94 95 // 96 //VOID 97 //ArmUpdateTranslationTableEntry ( 98 // IN VOID *TranslationTableEntry // R0 99 // IN VOID *MVA // R1 100 // ); 101 RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry 102 mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA 103 dsb 104 mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA 105 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp 106 dsb 107 isb 108 bx lr 109 110 RVCT_ASM_EXPORT ArmInvalidateTlb 111 mov r0,#0 112 mcr p15,0,r0,c8,c7,0 113 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp 114 dsb 115 isb 116 bx lr 117 118 RVCT_ASM_EXPORT ArmReadScr 119 mrc p15, 0, r0, c1, c1, 0 120 bx lr 121 122 RVCT_ASM_EXPORT ArmWriteScr 123 mcr p15, 0, r0, c1, c1, 0 124 bx lr 125 126 RVCT_ASM_EXPORT ArmReadHVBar 127 mrc p15, 4, r0, c12, c0, 0 128 bx lr 129 130 RVCT_ASM_EXPORT ArmWriteHVBar 131 mcr p15, 4, r0, c12, c0, 0 132 bx lr 133 134 RVCT_ASM_EXPORT ArmReadMVBar 135 mrc p15, 0, r0, c12, c0, 1 136 bx lr 137 138 RVCT_ASM_EXPORT ArmWriteMVBar 139 mcr p15, 0, r0, c12, c0, 1 140 bx lr 141 142 RVCT_ASM_EXPORT ArmCallWFE 143 wfe 144 bx lr 145 146 RVCT_ASM_EXPORT ArmCallSEV 147 sev 148 bx lr 149 150 RVCT_ASM_EXPORT ArmReadSctlr 151 mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data) 152 bx lr 153 154 155 RVCT_ASM_EXPORT ArmReadCpuActlr 156 mrc p15, 0, r0, c1, c0, 1 157 bx lr 158 159 RVCT_ASM_EXPORT ArmWriteCpuActlr 160 mcr p15, 0, r0, c1, c0, 1 161 dsb 162 isb 163 bx lr 164 165 END 166
