1 /** @file 2 PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI 3 Configuration cycles. Layers on PCI Express Library. 4 5 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php. 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 17 #include <Base.h> 18 19 #include <Library/PciLib.h> 20 #include <Library/PciExpressLib.h> 21 22 /** 23 Registers a PCI device so PCI configuration registers may be accessed after 24 SetVirtualAddressMap(). 25 26 Registers the PCI device specified by Address so all the PCI configuration registers 27 associated with that PCI device may be accessed after SetVirtualAddressMap() is called. 28 29 If Address > 0x0FFFFFFF, then ASSERT(). 30 31 @param Address The address that encodes the PCI Bus, Device, Function and 32 Register. 33 34 @retval RETURN_SUCCESS The PCI device was registered for runtime access. 35 @retval RETURN_UNSUPPORTED An attempt was made to call this function 36 after ExitBootServices(). 37 @retval RETURN_UNSUPPORTED The resources required to access the PCI device 38 at runtime could not be mapped. 39 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to 40 complete the registration. 41 42 **/ 43 RETURN_STATUS 44 EFIAPI 45 PciRegisterForRuntimeAccess ( 46 IN UINTN Address 47 ) 48 { 49 return PciExpressRegisterForRuntimeAccess (Address); 50 } 51 52 /** 53 Reads an 8-bit PCI configuration register. 54 55 Reads and returns the 8-bit PCI configuration register specified by Address. 56 This function must guarantee that all PCI read and write operations are 57 serialized. 58 59 If Address > 0x0FFFFFFF, then ASSERT(). 60 61 @param Address The address that encodes the PCI Bus, Device, Function and 62 Register. 63 64 @return The read value from the PCI configuration register. 65 66 **/ 67 UINT8 68 EFIAPI 69 PciRead8 ( 70 IN UINTN Address 71 ) 72 { 73 return PciExpressRead8 (Address); 74 } 75 76 /** 77 Writes an 8-bit PCI configuration register. 78 79 Writes the 8-bit PCI configuration register specified by Address with the 80 value specified by Value. Value is returned. This function must guarantee 81 that all PCI read and write operations are serialized. 82 83 If Address > 0x0FFFFFFF, then ASSERT(). 84 85 @param Address The address that encodes the PCI Bus, Device, Function and 86 Register. 87 @param Value The value to write. 88 89 @return The value written to the PCI configuration register. 90 91 **/ 92 UINT8 93 EFIAPI 94 PciWrite8 ( 95 IN UINTN Address, 96 IN UINT8 Value 97 ) 98 { 99 return PciExpressWrite8 (Address, Value); 100 } 101 102 /** 103 Performs a bitwise OR of an 8-bit PCI configuration register with 104 an 8-bit value. 105 106 Reads the 8-bit PCI configuration register specified by Address, performs a 107 bitwise OR between the read result and the value specified by 108 OrData, and writes the result to the 8-bit PCI configuration register 109 specified by Address. The value written to the PCI configuration register is 110 returned. This function must guarantee that all PCI read and write operations 111 are serialized. 112 113 If Address > 0x0FFFFFFF, then ASSERT(). 114 115 @param Address The address that encodes the PCI Bus, Device, Function and 116 Register. 117 @param OrData The value to OR with the PCI configuration register. 118 119 @return The value written back to the PCI configuration register. 120 121 **/ 122 UINT8 123 EFIAPI 124 PciOr8 ( 125 IN UINTN Address, 126 IN UINT8 OrData 127 ) 128 { 129 return PciExpressOr8 (Address, OrData); 130 } 131 132 /** 133 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 134 value. 135 136 Reads the 8-bit PCI configuration register specified by Address, performs a 137 bitwise AND between the read result and the value specified by AndData, and 138 writes the result to the 8-bit PCI configuration register specified by 139 Address. The value written to the PCI configuration register is returned. 140 This function must guarantee that all PCI read and write operations are 141 serialized. 142 143 If Address > 0x0FFFFFFF, then ASSERT(). 144 145 @param Address The address that encodes the PCI Bus, Device, Function and 146 Register. 147 @param AndData The value to AND with the PCI configuration register. 148 149 @return The value written back to the PCI configuration register. 150 151 **/ 152 UINT8 153 EFIAPI 154 PciAnd8 ( 155 IN UINTN Address, 156 IN UINT8 AndData 157 ) 158 { 159 return PciExpressAnd8 (Address, AndData); 160 } 161 162 /** 163 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 164 value, followed a bitwise OR with another 8-bit value. 165 166 Reads the 8-bit PCI configuration register specified by Address, performs a 167 bitwise AND between the read result and the value specified by AndData, 168 performs a bitwise OR between the result of the AND operation and 169 the value specified by OrData, and writes the result to the 8-bit PCI 170 configuration register specified by Address. The value written to the PCI 171 configuration register is returned. This function must guarantee that all PCI 172 read and write operations are serialized. 173 174 If Address > 0x0FFFFFFF, then ASSERT(). 175 176 @param Address The address that encodes the PCI Bus, Device, Function and 177 Register. 178 @param AndData The value to AND with the PCI configuration register. 179 @param OrData The value to OR with the result of the AND operation. 180 181 @return The value written back to the PCI configuration register. 182 183 **/ 184 UINT8 185 EFIAPI 186 PciAndThenOr8 ( 187 IN UINTN Address, 188 IN UINT8 AndData, 189 IN UINT8 OrData 190 ) 191 { 192 return PciExpressAndThenOr8 (Address, AndData, OrData); 193 } 194 195 /** 196 Reads a bit field of a PCI configuration register. 197 198 Reads the bit field in an 8-bit PCI configuration register. The bit field is 199 specified by the StartBit and the EndBit. The value of the bit field is 200 returned. 201 202 If Address > 0x0FFFFFFF, then ASSERT(). 203 If StartBit is greater than 7, then ASSERT(). 204 If EndBit is greater than 7, then ASSERT(). 205 If EndBit is less than StartBit, then ASSERT(). 206 207 @param Address The PCI configuration register to read. 208 @param StartBit The ordinal of the least significant bit in the bit field. 209 Range 0..7. 210 @param EndBit The ordinal of the most significant bit in the bit field. 211 Range 0..7. 212 213 @return The value of the bit field read from the PCI configuration register. 214 215 **/ 216 UINT8 217 EFIAPI 218 PciBitFieldRead8 ( 219 IN UINTN Address, 220 IN UINTN StartBit, 221 IN UINTN EndBit 222 ) 223 { 224 return PciExpressBitFieldRead8 (Address, StartBit, EndBit); 225 } 226 227 /** 228 Writes a bit field to a PCI configuration register. 229 230 Writes Value to the bit field of the PCI configuration register. The bit 231 field is specified by the StartBit and the EndBit. All other bits in the 232 destination PCI configuration register are preserved. The new value of the 233 8-bit register is returned. 234 235 If Address > 0x0FFFFFFF, then ASSERT(). 236 If StartBit is greater than 7, then ASSERT(). 237 If EndBit is greater than 7, then ASSERT(). 238 If EndBit is less than StartBit, then ASSERT(). 239 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 240 241 @param Address The PCI configuration register to write. 242 @param StartBit The ordinal of the least significant bit in the bit field. 243 Range 0..7. 244 @param EndBit The ordinal of the most significant bit in the bit field. 245 Range 0..7. 246 @param Value The new value of the bit field. 247 248 @return The value written back to the PCI configuration register. 249 250 **/ 251 UINT8 252 EFIAPI 253 PciBitFieldWrite8 ( 254 IN UINTN Address, 255 IN UINTN StartBit, 256 IN UINTN EndBit, 257 IN UINT8 Value 258 ) 259 { 260 return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value); 261 } 262 263 /** 264 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and 265 writes the result back to the bit field in the 8-bit port. 266 267 Reads the 8-bit PCI configuration register specified by Address, performs a 268 bitwise OR between the read result and the value specified by 269 OrData, and writes the result to the 8-bit PCI configuration register 270 specified by Address. The value written to the PCI configuration register is 271 returned. This function must guarantee that all PCI read and write operations 272 are serialized. Extra left bits in OrData are stripped. 273 274 If Address > 0x0FFFFFFF, then ASSERT(). 275 If StartBit is greater than 7, then ASSERT(). 276 If EndBit is greater than 7, then ASSERT(). 277 If EndBit is less than StartBit, then ASSERT(). 278 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 279 280 @param Address The PCI configuration register to write. 281 @param StartBit The ordinal of the least significant bit in the bit field. 282 Range 0..7. 283 @param EndBit The ordinal of the most significant bit in the bit field. 284 Range 0..7. 285 @param OrData The value to OR with the PCI configuration register. 286 287 @return The value written back to the PCI configuration register. 288 289 **/ 290 UINT8 291 EFIAPI 292 PciBitFieldOr8 ( 293 IN UINTN Address, 294 IN UINTN StartBit, 295 IN UINTN EndBit, 296 IN UINT8 OrData 297 ) 298 { 299 return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData); 300 } 301 302 /** 303 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise 304 AND, and writes the result back to the bit field in the 8-bit register. 305 306 Reads the 8-bit PCI configuration register specified by Address, performs a 307 bitwise AND between the read result and the value specified by AndData, and 308 writes the result to the 8-bit PCI configuration register specified by 309 Address. The value written to the PCI configuration register is returned. 310 This function must guarantee that all PCI read and write operations are 311 serialized. Extra left bits in AndData are stripped. 312 313 If Address > 0x0FFFFFFF, then ASSERT(). 314 If StartBit is greater than 7, then ASSERT(). 315 If EndBit is greater than 7, then ASSERT(). 316 If EndBit is less than StartBit, then ASSERT(). 317 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 318 319 @param Address The PCI configuration register to write. 320 @param StartBit The ordinal of the least significant bit in the bit field. 321 Range 0..7. 322 @param EndBit The ordinal of the most significant bit in the bit field. 323 Range 0..7. 324 @param AndData The value to AND with the PCI configuration register. 325 326 @return The value written back to the PCI configuration register. 327 328 **/ 329 UINT8 330 EFIAPI 331 PciBitFieldAnd8 ( 332 IN UINTN Address, 333 IN UINTN StartBit, 334 IN UINTN EndBit, 335 IN UINT8 AndData 336 ) 337 { 338 return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData); 339 } 340 341 /** 342 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a 343 bitwise OR, and writes the result back to the bit field in the 344 8-bit port. 345 346 Reads the 8-bit PCI configuration register specified by Address, performs a 347 bitwise AND followed by a bitwise OR between the read result and 348 the value specified by AndData, and writes the result to the 8-bit PCI 349 configuration register specified by Address. The value written to the PCI 350 configuration register is returned. This function must guarantee that all PCI 351 read and write operations are serialized. Extra left bits in both AndData and 352 OrData are stripped. 353 354 If Address > 0x0FFFFFFF, then ASSERT(). 355 If StartBit is greater than 7, then ASSERT(). 356 If EndBit is greater than 7, then ASSERT(). 357 If EndBit is less than StartBit, then ASSERT(). 358 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 359 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 360 361 @param Address The PCI configuration register to write. 362 @param StartBit The ordinal of the least significant bit in the bit field. 363 Range 0..7. 364 @param EndBit The ordinal of the most significant bit in the bit field. 365 Range 0..7. 366 @param AndData The value to AND with the PCI configuration register. 367 @param OrData The value to OR with the result of the AND operation. 368 369 @return The value written back to the PCI configuration register. 370 371 **/ 372 UINT8 373 EFIAPI 374 PciBitFieldAndThenOr8 ( 375 IN UINTN Address, 376 IN UINTN StartBit, 377 IN UINTN EndBit, 378 IN UINT8 AndData, 379 IN UINT8 OrData 380 ) 381 { 382 return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData); 383 } 384 385 /** 386 Reads a 16-bit PCI configuration register. 387 388 Reads and returns the 16-bit PCI configuration register specified by Address. 389 This function must guarantee that all PCI read and write operations are 390 serialized. 391 392 If Address > 0x0FFFFFFF, then ASSERT(). 393 If Address is not aligned on a 16-bit boundary, then ASSERT(). 394 395 @param Address The address that encodes the PCI Bus, Device, Function and 396 Register. 397 398 @return The read value from the PCI configuration register. 399 400 **/ 401 UINT16 402 EFIAPI 403 PciRead16 ( 404 IN UINTN Address 405 ) 406 { 407 return PciExpressRead16 (Address); 408 } 409 410 /** 411 Writes a 16-bit PCI configuration register. 412 413 Writes the 16-bit PCI configuration register specified by Address with the 414 value specified by Value. Value is returned. This function must guarantee 415 that all PCI read and write operations are serialized. 416 417 If Address > 0x0FFFFFFF, then ASSERT(). 418 If Address is not aligned on a 16-bit boundary, then ASSERT(). 419 420 @param Address The address that encodes the PCI Bus, Device, Function and 421 Register. 422 @param Value The value to write. 423 424 @return The value written to the PCI configuration register. 425 426 **/ 427 UINT16 428 EFIAPI 429 PciWrite16 ( 430 IN UINTN Address, 431 IN UINT16 Value 432 ) 433 { 434 return PciExpressWrite16 (Address, Value); 435 } 436 437 /** 438 Performs a bitwise OR of a 16-bit PCI configuration register with 439 a 16-bit value. 440 441 Reads the 16-bit PCI configuration register specified by Address, performs a 442 bitwise OR between the read result and the value specified by 443 OrData, and writes the result to the 16-bit PCI configuration register 444 specified by Address. The value written to the PCI configuration register is 445 returned. This function must guarantee that all PCI read and write operations 446 are serialized. 447 448 If Address > 0x0FFFFFFF, then ASSERT(). 449 If Address is not aligned on a 16-bit boundary, then ASSERT(). 450 451 @param Address The address that encodes the PCI Bus, Device, Function and 452 Register. 453 @param OrData The value to OR with the PCI configuration register. 454 455 @return The value written back to the PCI configuration register. 456 457 **/ 458 UINT16 459 EFIAPI 460 PciOr16 ( 461 IN UINTN Address, 462 IN UINT16 OrData 463 ) 464 { 465 return PciExpressOr16 (Address, OrData); 466 } 467 468 /** 469 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 470 value. 471 472 Reads the 16-bit PCI configuration register specified by Address, performs a 473 bitwise AND between the read result and the value specified by AndData, and 474 writes the result to the 16-bit PCI configuration register specified by 475 Address. The value written to the PCI configuration register is returned. 476 This function must guarantee that all PCI read and write operations are 477 serialized. 478 479 If Address > 0x0FFFFFFF, then ASSERT(). 480 If Address is not aligned on a 16-bit boundary, then ASSERT(). 481 482 @param Address The address that encodes the PCI Bus, Device, Function and 483 Register. 484 @param AndData The value to AND with the PCI configuration register. 485 486 @return The value written back to the PCI configuration register. 487 488 **/ 489 UINT16 490 EFIAPI 491 PciAnd16 ( 492 IN UINTN Address, 493 IN UINT16 AndData 494 ) 495 { 496 return PciExpressAnd16 (Address, AndData); 497 } 498 499 /** 500 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 501 value, followed a bitwise OR with another 16-bit value. 502 503 Reads the 16-bit PCI configuration register specified by Address, performs a 504 bitwise AND between the read result and the value specified by AndData, 505 performs a bitwise OR between the result of the AND operation and 506 the value specified by OrData, and writes the result to the 16-bit PCI 507 configuration register specified by Address. The value written to the PCI 508 configuration register is returned. This function must guarantee that all PCI 509 read and write operations are serialized. 510 511 If Address > 0x0FFFFFFF, then ASSERT(). 512 If Address is not aligned on a 16-bit boundary, then ASSERT(). 513 514 @param Address The address that encodes the PCI Bus, Device, Function and 515 Register. 516 @param AndData The value to AND with the PCI configuration register. 517 @param OrData The value to OR with the result of the AND operation. 518 519 @return The value written back to the PCI configuration register. 520 521 **/ 522 UINT16 523 EFIAPI 524 PciAndThenOr16 ( 525 IN UINTN Address, 526 IN UINT16 AndData, 527 IN UINT16 OrData 528 ) 529 { 530 return PciExpressAndThenOr16 (Address, AndData, OrData); 531 } 532 533 /** 534 Reads a bit field of a PCI configuration register. 535 536 Reads the bit field in a 16-bit PCI configuration register. The bit field is 537 specified by the StartBit and the EndBit. The value of the bit field is 538 returned. 539 540 If Address > 0x0FFFFFFF, then ASSERT(). 541 If Address is not aligned on a 16-bit boundary, then ASSERT(). 542 If StartBit is greater than 15, then ASSERT(). 543 If EndBit is greater than 15, then ASSERT(). 544 If EndBit is less than StartBit, then ASSERT(). 545 546 @param Address The PCI configuration register to read. 547 @param StartBit The ordinal of the least significant bit in the bit field. 548 Range 0..15. 549 @param EndBit The ordinal of the most significant bit in the bit field. 550 Range 0..15. 551 552 @return The value of the bit field read from the PCI configuration register. 553 554 **/ 555 UINT16 556 EFIAPI 557 PciBitFieldRead16 ( 558 IN UINTN Address, 559 IN UINTN StartBit, 560 IN UINTN EndBit 561 ) 562 { 563 return PciExpressBitFieldRead16 (Address, StartBit, EndBit); 564 } 565 566 /** 567 Writes a bit field to a PCI configuration register. 568 569 Writes Value to the bit field of the PCI configuration register. The bit 570 field is specified by the StartBit and the EndBit. All other bits in the 571 destination PCI configuration register are preserved. The new value of the 572 16-bit register is returned. 573 574 If Address > 0x0FFFFFFF, then ASSERT(). 575 If Address is not aligned on a 16-bit boundary, then ASSERT(). 576 If StartBit is greater than 15, then ASSERT(). 577 If EndBit is greater than 15, then ASSERT(). 578 If EndBit is less than StartBit, then ASSERT(). 579 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 580 581 @param Address The PCI configuration register to write. 582 @param StartBit The ordinal of the least significant bit in the bit field. 583 Range 0..15. 584 @param EndBit The ordinal of the most significant bit in the bit field. 585 Range 0..15. 586 @param Value The new value of the bit field. 587 588 @return The value written back to the PCI configuration register. 589 590 **/ 591 UINT16 592 EFIAPI 593 PciBitFieldWrite16 ( 594 IN UINTN Address, 595 IN UINTN StartBit, 596 IN UINTN EndBit, 597 IN UINT16 Value 598 ) 599 { 600 return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value); 601 } 602 603 /** 604 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and 605 writes the result back to the bit field in the 16-bit port. 606 607 Reads the 16-bit PCI configuration register specified by Address, performs a 608 bitwise OR between the read result and the value specified by 609 OrData, and writes the result to the 16-bit PCI configuration register 610 specified by Address. The value written to the PCI configuration register is 611 returned. This function must guarantee that all PCI read and write operations 612 are serialized. Extra left bits in OrData are stripped. 613 614 If Address > 0x0FFFFFFF, then ASSERT(). 615 If Address is not aligned on a 16-bit boundary, then ASSERT(). 616 If StartBit is greater than 15, then ASSERT(). 617 If EndBit is greater than 15, then ASSERT(). 618 If EndBit is less than StartBit, then ASSERT(). 619 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 620 621 @param Address The PCI configuration register to write. 622 @param StartBit The ordinal of the least significant bit in the bit field. 623 Range 0..15. 624 @param EndBit The ordinal of the most significant bit in the bit field. 625 Range 0..15. 626 @param OrData The value to OR with the PCI configuration register. 627 628 @return The value written back to the PCI configuration register. 629 630 **/ 631 UINT16 632 EFIAPI 633 PciBitFieldOr16 ( 634 IN UINTN Address, 635 IN UINTN StartBit, 636 IN UINTN EndBit, 637 IN UINT16 OrData 638 ) 639 { 640 return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData); 641 } 642 643 /** 644 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise 645 AND, and writes the result back to the bit field in the 16-bit register. 646 647 Reads the 16-bit PCI configuration register specified by Address, performs a 648 bitwise AND between the read result and the value specified by AndData, and 649 writes the result to the 16-bit PCI configuration register specified by 650 Address. The value written to the PCI configuration register is returned. 651 This function must guarantee that all PCI read and write operations are 652 serialized. Extra left bits in AndData are stripped. 653 654 If Address > 0x0FFFFFFF, then ASSERT(). 655 If Address is not aligned on a 16-bit boundary, then ASSERT(). 656 If StartBit is greater than 15, then ASSERT(). 657 If EndBit is greater than 15, then ASSERT(). 658 If EndBit is less than StartBit, then ASSERT(). 659 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 660 661 @param Address The PCI configuration register to write. 662 @param StartBit The ordinal of the least significant bit in the bit field. 663 Range 0..15. 664 @param EndBit The ordinal of the most significant bit in the bit field. 665 Range 0..15. 666 @param AndData The value to AND with the PCI configuration register. 667 668 @return The value written back to the PCI configuration register. 669 670 **/ 671 UINT16 672 EFIAPI 673 PciBitFieldAnd16 ( 674 IN UINTN Address, 675 IN UINTN StartBit, 676 IN UINTN EndBit, 677 IN UINT16 AndData 678 ) 679 { 680 return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData); 681 } 682 683 /** 684 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a 685 bitwise OR, and writes the result back to the bit field in the 686 16-bit port. 687 688 Reads the 16-bit PCI configuration register specified by Address, performs a 689 bitwise AND followed by a bitwise OR between the read result and 690 the value specified by AndData, and writes the result to the 16-bit PCI 691 configuration register specified by Address. The value written to the PCI 692 configuration register is returned. This function must guarantee that all PCI 693 read and write operations are serialized. Extra left bits in both AndData and 694 OrData are stripped. 695 696 If Address > 0x0FFFFFFF, then ASSERT(). 697 If Address is not aligned on a 16-bit boundary, then ASSERT(). 698 If StartBit is greater than 15, then ASSERT(). 699 If EndBit is greater than 15, then ASSERT(). 700 If EndBit is less than StartBit, then ASSERT(). 701 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 702 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 703 704 @param Address The PCI configuration register to write. 705 @param StartBit The ordinal of the least significant bit in the bit field. 706 Range 0..15. 707 @param EndBit The ordinal of the most significant bit in the bit field. 708 Range 0..15. 709 @param AndData The value to AND with the PCI configuration register. 710 @param OrData The value to OR with the result of the AND operation. 711 712 @return The value written back to the PCI configuration register. 713 714 **/ 715 UINT16 716 EFIAPI 717 PciBitFieldAndThenOr16 ( 718 IN UINTN Address, 719 IN UINTN StartBit, 720 IN UINTN EndBit, 721 IN UINT16 AndData, 722 IN UINT16 OrData 723 ) 724 { 725 return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData); 726 } 727 728 /** 729 Reads a 32-bit PCI configuration register. 730 731 Reads and returns the 32-bit PCI configuration register specified by Address. 732 This function must guarantee that all PCI read and write operations are 733 serialized. 734 735 If Address > 0x0FFFFFFF, then ASSERT(). 736 If Address is not aligned on a 32-bit boundary, then ASSERT(). 737 738 @param Address The address that encodes the PCI Bus, Device, Function and 739 Register. 740 741 @return The read value from the PCI configuration register. 742 743 **/ 744 UINT32 745 EFIAPI 746 PciRead32 ( 747 IN UINTN Address 748 ) 749 { 750 return PciExpressRead32 (Address); 751 } 752 753 /** 754 Writes a 32-bit PCI configuration register. 755 756 Writes the 32-bit PCI configuration register specified by Address with the 757 value specified by Value. Value is returned. This function must guarantee 758 that all PCI read and write operations are serialized. 759 760 If Address > 0x0FFFFFFF, then ASSERT(). 761 If Address is not aligned on a 32-bit boundary, then ASSERT(). 762 763 @param Address The address that encodes the PCI Bus, Device, Function and 764 Register. 765 @param Value The value to write. 766 767 @return The value written to the PCI configuration register. 768 769 **/ 770 UINT32 771 EFIAPI 772 PciWrite32 ( 773 IN UINTN Address, 774 IN UINT32 Value 775 ) 776 { 777 return PciExpressWrite32 (Address, Value); 778 } 779 780 /** 781 Performs a bitwise OR of a 32-bit PCI configuration register with 782 a 32-bit value. 783 784 Reads the 32-bit PCI configuration register specified by Address, performs a 785 bitwise OR between the read result and the value specified by 786 OrData, and writes the result to the 32-bit PCI configuration register 787 specified by Address. The value written to the PCI configuration register is 788 returned. This function must guarantee that all PCI read and write operations 789 are serialized. 790 791 If Address > 0x0FFFFFFF, then ASSERT(). 792 If Address is not aligned on a 32-bit boundary, then ASSERT(). 793 794 @param Address The address that encodes the PCI Bus, Device, Function and 795 Register. 796 @param OrData The value to OR with the PCI configuration register. 797 798 @return The value written back to the PCI configuration register. 799 800 **/ 801 UINT32 802 EFIAPI 803 PciOr32 ( 804 IN UINTN Address, 805 IN UINT32 OrData 806 ) 807 { 808 return PciExpressOr32 (Address, OrData); 809 } 810 811 /** 812 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 813 value. 814 815 Reads the 32-bit PCI configuration register specified by Address, performs a 816 bitwise AND between the read result and the value specified by AndData, and 817 writes the result to the 32-bit PCI configuration register specified by 818 Address. The value written to the PCI configuration register is returned. 819 This function must guarantee that all PCI read and write operations are 820 serialized. 821 822 If Address > 0x0FFFFFFF, then ASSERT(). 823 If Address is not aligned on a 32-bit boundary, then ASSERT(). 824 825 @param Address The address that encodes the PCI Bus, Device, Function and 826 Register. 827 @param AndData The value to AND with the PCI configuration register. 828 829 @return The value written back to the PCI configuration register. 830 831 **/ 832 UINT32 833 EFIAPI 834 PciAnd32 ( 835 IN UINTN Address, 836 IN UINT32 AndData 837 ) 838 { 839 return PciExpressAnd32 (Address, AndData); 840 } 841 842 /** 843 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 844 value, followed a bitwise OR with another 32-bit value. 845 846 Reads the 32-bit PCI configuration register specified by Address, performs a 847 bitwise AND between the read result and the value specified by AndData, 848 performs a bitwise OR between the result of the AND operation and 849 the value specified by OrData, and writes the result to the 32-bit PCI 850 configuration register specified by Address. The value written to the PCI 851 configuration register is returned. This function must guarantee that all PCI 852 read and write operations are serialized. 853 854 If Address > 0x0FFFFFFF, then ASSERT(). 855 If Address is not aligned on a 32-bit boundary, then ASSERT(). 856 857 @param Address The address that encodes the PCI Bus, Device, Function and 858 Register. 859 @param AndData The value to AND with the PCI configuration register. 860 @param OrData The value to OR with the result of the AND operation. 861 862 @return The value written back to the PCI configuration register. 863 864 **/ 865 UINT32 866 EFIAPI 867 PciAndThenOr32 ( 868 IN UINTN Address, 869 IN UINT32 AndData, 870 IN UINT32 OrData 871 ) 872 { 873 return PciExpressAndThenOr32 (Address, AndData, OrData); 874 } 875 876 /** 877 Reads a bit field of a PCI configuration register. 878 879 Reads the bit field in a 32-bit PCI configuration register. The bit field is 880 specified by the StartBit and the EndBit. The value of the bit field is 881 returned. 882 883 If Address > 0x0FFFFFFF, then ASSERT(). 884 If Address is not aligned on a 32-bit boundary, then ASSERT(). 885 If StartBit is greater than 31, then ASSERT(). 886 If EndBit is greater than 31, then ASSERT(). 887 If EndBit is less than StartBit, then ASSERT(). 888 889 @param Address The PCI configuration register to read. 890 @param StartBit The ordinal of the least significant bit in the bit field. 891 Range 0..31. 892 @param EndBit The ordinal of the most significant bit in the bit field. 893 Range 0..31. 894 895 @return The value of the bit field read from the PCI configuration register. 896 897 **/ 898 UINT32 899 EFIAPI 900 PciBitFieldRead32 ( 901 IN UINTN Address, 902 IN UINTN StartBit, 903 IN UINTN EndBit 904 ) 905 { 906 return PciExpressBitFieldRead32 (Address, StartBit, EndBit); 907 } 908 909 /** 910 Writes a bit field to a PCI configuration register. 911 912 Writes Value to the bit field of the PCI configuration register. The bit 913 field is specified by the StartBit and the EndBit. All other bits in the 914 destination PCI configuration register are preserved. The new value of the 915 32-bit register is returned. 916 917 If Address > 0x0FFFFFFF, then ASSERT(). 918 If Address is not aligned on a 32-bit boundary, then ASSERT(). 919 If StartBit is greater than 31, then ASSERT(). 920 If EndBit is greater than 31, then ASSERT(). 921 If EndBit is less than StartBit, then ASSERT(). 922 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 923 924 @param Address The PCI configuration register to write. 925 @param StartBit The ordinal of the least significant bit in the bit field. 926 Range 0..31. 927 @param EndBit The ordinal of the most significant bit in the bit field. 928 Range 0..31. 929 @param Value The new value of the bit field. 930 931 @return The value written back to the PCI configuration register. 932 933 **/ 934 UINT32 935 EFIAPI 936 PciBitFieldWrite32 ( 937 IN UINTN Address, 938 IN UINTN StartBit, 939 IN UINTN EndBit, 940 IN UINT32 Value 941 ) 942 { 943 return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value); 944 } 945 946 /** 947 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and 948 writes the result back to the bit field in the 32-bit port. 949 950 Reads the 32-bit PCI configuration register specified by Address, performs a 951 bitwise OR between the read result and the value specified by 952 OrData, and writes the result to the 32-bit PCI configuration register 953 specified by Address. The value written to the PCI configuration register is 954 returned. This function must guarantee that all PCI read and write operations 955 are serialized. Extra left bits in OrData are stripped. 956 957 If Address > 0x0FFFFFFF, then ASSERT(). 958 If Address is not aligned on a 32-bit boundary, then ASSERT(). 959 If StartBit is greater than 31, then ASSERT(). 960 If EndBit is greater than 31, then ASSERT(). 961 If EndBit is less than StartBit, then ASSERT(). 962 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 963 964 @param Address The PCI configuration register to write. 965 @param StartBit The ordinal of the least significant bit in the bit field. 966 Range 0..31. 967 @param EndBit The ordinal of the most significant bit in the bit field. 968 Range 0..31. 969 @param OrData The value to OR with the PCI configuration register. 970 971 @return The value written back to the PCI configuration register. 972 973 **/ 974 UINT32 975 EFIAPI 976 PciBitFieldOr32 ( 977 IN UINTN Address, 978 IN UINTN StartBit, 979 IN UINTN EndBit, 980 IN UINT32 OrData 981 ) 982 { 983 return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData); 984 } 985 986 /** 987 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise 988 AND, and writes the result back to the bit field in the 32-bit register. 989 990 Reads the 32-bit PCI configuration register specified by Address, performs a 991 bitwise AND between the read result and the value specified by AndData, and 992 writes the result to the 32-bit PCI configuration register specified by 993 Address. The value written to the PCI configuration register is returned. 994 This function must guarantee that all PCI read and write operations are 995 serialized. Extra left bits in AndData are stripped. 996 997 If Address > 0x0FFFFFFF, then ASSERT(). 998 If Address is not aligned on a 32-bit boundary, then ASSERT(). 999 If StartBit is greater than 31, then ASSERT(). 1000 If EndBit is greater than 31, then ASSERT(). 1001 If EndBit is less than StartBit, then ASSERT(). 1002 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 1003 1004 @param Address The PCI configuration register to write. 1005 @param StartBit The ordinal of the least significant bit in the bit field. 1006 Range 0..31. 1007 @param EndBit The ordinal of the most significant bit in the bit field. 1008 Range 0..31. 1009 @param AndData The value to AND with the PCI configuration register. 1010 1011 @return The value written back to the PCI configuration register. 1012 1013 **/ 1014 UINT32 1015 EFIAPI 1016 PciBitFieldAnd32 ( 1017 IN UINTN Address, 1018 IN UINTN StartBit, 1019 IN UINTN EndBit, 1020 IN UINT32 AndData 1021 ) 1022 { 1023 return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData); 1024 } 1025 1026 /** 1027 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a 1028 bitwise OR, and writes the result back to the bit field in the 1029 32-bit port. 1030 1031 Reads the 32-bit PCI configuration register specified by Address, performs a 1032 bitwise AND followed by a bitwise OR between the read result and 1033 the value specified by AndData, and writes the result to the 32-bit PCI 1034 configuration register specified by Address. The value written to the PCI 1035 configuration register is returned. This function must guarantee that all PCI 1036 read and write operations are serialized. Extra left bits in both AndData and 1037 OrData are stripped. 1038 1039 If Address > 0x0FFFFFFF, then ASSERT(). 1040 If Address is not aligned on a 32-bit boundary, then ASSERT(). 1041 If StartBit is greater than 31, then ASSERT(). 1042 If EndBit is greater than 31, then ASSERT(). 1043 If EndBit is less than StartBit, then ASSERT(). 1044 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 1045 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 1046 1047 @param Address The PCI configuration register to write. 1048 @param StartBit The ordinal of the least significant bit in the bit field. 1049 Range 0..31. 1050 @param EndBit The ordinal of the most significant bit in the bit field. 1051 Range 0..31. 1052 @param AndData The value to AND with the PCI configuration register. 1053 @param OrData The value to OR with the result of the AND operation. 1054 1055 @return The value written back to the PCI configuration register. 1056 1057 **/ 1058 UINT32 1059 EFIAPI 1060 PciBitFieldAndThenOr32 ( 1061 IN UINTN Address, 1062 IN UINTN StartBit, 1063 IN UINTN EndBit, 1064 IN UINT32 AndData, 1065 IN UINT32 OrData 1066 ) 1067 { 1068 return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData); 1069 } 1070 1071 /** 1072 Reads a range of PCI configuration registers into a caller supplied buffer. 1073 1074 Reads the range of PCI configuration registers specified by StartAddress and 1075 Size into the buffer specified by Buffer. This function only allows the PCI 1076 configuration registers from a single PCI function to be read. Size is 1077 returned. When possible 32-bit PCI configuration read cycles are used to read 1078 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit 1079 and 16-bit PCI configuration read cycles may be used at the beginning and the 1080 end of the range. 1081 1082 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1083 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1084 If Size > 0 and Buffer is NULL, then ASSERT(). 1085 1086 @param StartAddress The starting address that encodes the PCI Bus, Device, 1087 Function and Register. 1088 @param Size The size in bytes of the transfer. 1089 @param Buffer The pointer to a buffer receiving the data read. 1090 1091 @return Size 1092 1093 **/ 1094 UINTN 1095 EFIAPI 1096 PciReadBuffer ( 1097 IN UINTN StartAddress, 1098 IN UINTN Size, 1099 OUT VOID *Buffer 1100 ) 1101 { 1102 return PciExpressReadBuffer (StartAddress, Size, Buffer); 1103 } 1104 1105 /** 1106 Copies the data in a caller supplied buffer to a specified range of PCI 1107 configuration space. 1108 1109 Writes the range of PCI configuration registers specified by StartAddress and 1110 Size from the buffer specified by Buffer. This function only allows the PCI 1111 configuration registers from a single PCI function to be written. Size is 1112 returned. When possible 32-bit PCI configuration write cycles are used to 1113 write from StartAdress to StartAddress + Size. Due to alignment restrictions, 1114 8-bit and 16-bit PCI configuration write cycles may be used at the beginning 1115 and the end of the range. 1116 1117 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1118 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1119 If Size > 0 and Buffer is NULL, then ASSERT(). 1120 1121 @param StartAddress The starting address that encodes the PCI Bus, Device, 1122 Function and Register. 1123 @param Size The size in bytes of the transfer. 1124 @param Buffer The pointer to a buffer containing the data to write. 1125 1126 @return Size written to StartAddress. 1127 1128 **/ 1129 UINTN 1130 EFIAPI 1131 PciWriteBuffer ( 1132 IN UINTN StartAddress, 1133 IN UINTN Size, 1134 IN VOID *Buffer 1135 ) 1136 { 1137 return PciExpressWriteBuffer (StartAddress, Size, Buffer); 1138 } 1139
