1 /** 2 **/ 3 /** 4 5 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved 6 7 This program and the accompanying materials are licensed and made available under 8 the terms and conditions of the BSD License that accompanies this distribution. 9 The full text of the license may be found at 10 http://opensource.org/licenses/bsd-license.php. 11 12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 15 16 17 @file 18 PchS3Support.h 19 20 @brief 21 This file defines the PCH S3 support Protocol. 22 23 **/ 24 #ifndef _PCH_S3_SUPPORT_PROTOCOL_H_ 25 #define _PCH_S3_SUPPORT_PROTOCOL_H_ 26 27 #ifndef ECP_FLAG 28 #include <Pi/PiS3BootScript.h> 29 #endif 30 31 #define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \ 32 { \ 33 0xe287d20b, 0xd897, 0x4e1e, 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 \ 34 } 35 36 #include <Protocol/PchPlatformPolicy.h> 37 38 /// 39 /// Extern the GUID for protocol users. 40 /// 41 extern EFI_GUID gEfiPchS3SupportProtocolGuid; 42 43 /// 44 /// Forward reference for ANSI C compatibility 45 /// 46 typedef struct _EFI_PCH_S3_SUPPORT_PROTOCOL EFI_PCH_S3_SUPPORT_PROTOCOL; 47 48 typedef enum { 49 PchS3ItemTypeSendCodecCommand, 50 PchS3ItemTypePollStatus, 51 PchS3ItemTypeInitPcieRootPortDownstream, 52 PchS3ItemTypePcieSetPm, 53 PchS3ItemTypePmTimerStall, 54 PchS3ItemTypeMax 55 } EFI_PCH_S3_DISPATCH_ITEM_TYPE; 56 57 /// 58 /// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI 59 /// plug 4 to ParameterSize in PEIM if you really need it 60 /// 61 typedef struct { 62 UINT32 HdaBar; 63 UINT32 CodecCmdData; 64 } EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND; 65 66 typedef struct { 67 UINT64 MmioAddress; 68 EFI_BOOT_SCRIPT_WIDTH Width; 69 UINT64 Mask; 70 UINT64 Value; 71 UINT32 Timeout; // us 72 } EFI_PCH_S3_PARAMETER_POLL_STATUS; 73 74 typedef struct { 75 UINT8 RootPortBus; 76 UINT8 RootPortDevice; 77 UINT8 RootPortFunc; 78 UINT8 TempBusNumberMin; 79 UINT8 TempBusNumberMax; 80 } EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM; 81 82 typedef struct { 83 UINT8 RootPortBus; 84 UINT8 RootPortDevice; 85 UINT8 RootPortFunc; 86 PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm; 87 UINT8 NumOfDevAspmOverride; 88 UINT32 DevAspmOverrideAddr; 89 UINT8 TempBusNumberMin; 90 UINT8 TempBusNumberMax; 91 UINT8 NumOfDevLtrOverride; 92 UINT32 DevLtrOverrideAddr; 93 } EFI_PCH_S3_PARAMETER_PCIE_SET_PM; 94 95 typedef struct { 96 UINT32 DelayTime; // us 97 } EFI_PCH_S3_PARAMETER_PM_TIMER_STALL; 98 99 typedef struct { 100 EFI_PCH_S3_DISPATCH_ITEM_TYPE Type; 101 VOID *Parameter; 102 } EFI_PCH_S3_DISPATCH_ITEM; 103 104 /// 105 /// Member functions 106 /// 107 typedef 108 EFI_STATUS 109 (EFIAPI *EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM) ( 110 IN EFI_PCH_S3_SUPPORT_PROTOCOL * This, 111 IN EFI_PCH_S3_DISPATCH_ITEM * DispatchItem, 112 OUT EFI_PHYSICAL_ADDRESS * S3DispatchEntryPoint 113 ); 114 115 /** 116 117 @brief 118 Set an item to be dispatched at S3 resume time. At the same time, the entry point 119 of the PCH S3 support image is returned to be used in subsequent boot script save 120 call 121 122 @param[in] This Pointer to the protocol instance. 123 @param[in] DispatchItem The item to be dispatched. 124 @param[in] S3DispatchEntryPoint The entry point of the PCH S3 support image. 125 126 @retval EFI_STATUS Successfully completed. 127 @retval EFI_OUT_OF_RESOURCES Out of resources. 128 129 **/ 130 131 /// 132 /// Protocol definition 133 /// 134 struct _EFI_PCH_S3_SUPPORT_PROTOCOL { 135 EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem; 136 }; 137 138 #endif 139
