1 /* 2 3 Copyright (c) 2009, 2010, 2011 STMicroelectronics 4 Written by Christophe Lyon 5 6 Permission is hereby granted, free of charge, to any person obtaining a copy 7 of this software and associated documentation files (the "Software"), to deal 8 in the Software without restriction, including without limitation the rights 9 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 copies of the Software, and to permit persons to whom the Software is 11 furnished to do so, subject to the following conditions: 12 13 The above copyright notice and this permission notice shall be included in 14 all copies or substantial portions of the Software. 15 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 THE SOFTWARE. 23 24 */ 25 26 #if defined(__arm__) || defined(__aarch64__) 27 #include <arm_neon.h> 28 #else 29 #include "stm-arm-neon.h" 30 #endif 31 32 #include "stm-arm-neon-ref.h" 33 34 #define TEST_MSG "VSRA_N" 35 void exec_vsra_n (void) 36 { 37 /* Basic test: y=vsra_n(x,v), then store the result. */ 38 #define TEST_VSRA_N(Q, T1, T2, W, N, V) \ 39 VECT_VAR(vector_res, T1, W, N) = \ 40 vsra##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \ 41 VECT_VAR(vector2, T1, W, N), \ 42 V); \ 43 vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N)) 44 45 /* With ARM RVCT, we need to declare variables before any executable 46 statement */ 47 48 DECL_VARIABLE_ALL_VARIANTS(vector); 49 DECL_VARIABLE_ALL_VARIANTS(vector2); 50 DECL_VARIABLE_ALL_VARIANTS(vector_res); 51 52 clean_results (); 53 54 /* Initialize input "vector" from "buffer" */ 55 TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer); 56 57 /* Choose arbitrary initialization values */ 58 VDUP(vector2, , int, s, 8, 8, 0x11); 59 VDUP(vector2, , int, s, 16, 4, 0x22); 60 VDUP(vector2, , int, s, 32, 2, 0x33); 61 VDUP(vector2, , int, s, 64, 1, 0x44); 62 VDUP(vector2, , uint, u, 8, 8, 0x55); 63 VDUP(vector2, , uint, u, 16, 4, 0x66); 64 VDUP(vector2, , uint, u, 32, 2, 0x77); 65 VDUP(vector2, , uint, u, 64, 1, 0x88); 66 67 VDUP(vector2, q, int, s, 8, 16, 0x11); 68 VDUP(vector2, q, int, s, 16, 8, 0x22); 69 VDUP(vector2, q, int, s, 32, 4, 0x33); 70 VDUP(vector2, q, int, s, 64, 2, 0x44); 71 VDUP(vector2, q, uint, u, 8, 16, 0x55); 72 VDUP(vector2, q, uint, u, 16, 8, 0x66); 73 VDUP(vector2, q, uint, u, 32, 4, 0x77); 74 VDUP(vector2, q, uint, u, 64, 2, 0x88); 75 76 /* Choose shift amount arbitrarily */ 77 TEST_VSRA_N(, int, s, 8, 8, 1); 78 TEST_VSRA_N(, int, s, 16, 4, 12); 79 TEST_VSRA_N(, int, s, 32, 2, 2); 80 TEST_VSRA_N(, int, s, 64, 1, 32); 81 TEST_VSRA_N(, uint, u, 8, 8, 2); 82 TEST_VSRA_N(, uint, u, 16, 4, 3); 83 TEST_VSRA_N(, uint, u, 32, 2, 5); 84 TEST_VSRA_N(, uint, u, 64, 1, 33); 85 86 TEST_VSRA_N(q, int, s, 8, 16, 1); 87 TEST_VSRA_N(q, int, s, 16, 8, 12); 88 TEST_VSRA_N(q, int, s, 32, 4, 2); 89 TEST_VSRA_N(q, int, s, 64, 2, 32); 90 TEST_VSRA_N(q, uint, u, 8, 16, 2); 91 TEST_VSRA_N(q, uint, u, 16, 8, 3); 92 TEST_VSRA_N(q, uint, u, 32, 4, 5); 93 TEST_VSRA_N(q, uint, u, 64, 2, 33); 94 95 /* FIXME: only a few result buffers are used, but we output all of them */ 96 dump_results_hex (TEST_MSG); 97 } 98
