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config.guess06-Dec-201743.5K
config.h.in06-Dec-2017522
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configure06-Dec-2017126.6K
configure.in06-Dec-20171.9K
cpu_features.s06-Dec-2017184
cpu_mode_ppc.c06-Dec-2017955
cpu_mode_x86.c06-Dec-2017853
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decode_rs.h06-Dec-20178.2K
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dotprod.c06-Dec-20171.8K
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fec.c06-Dec-20171.3K
fec.h06-Dec-201712.9K
fixed.h06-Dec-2017785
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sqtest.c06-Dec-2017883
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README

      1 COPYRIGHT
      2 
      3 This package is copyright 2006 by Phil Karn, KA9Q. It may be used
      4 under the terms of the GNU Lesser General Public License (LGPL). See
      5 the file "lesser.txt" in this package for license details.
      6 
      7 INTRODUCTION
      8 
      9 This package provides a set of functions that implement several
     10 popular forward error correction (FEC) algorithms and several low-level routines
     11 useful in modems implemented with digital signal processing (DSP).
     12 
     13 The following routines are provided:
     14 
     15 1. Viterbi decoders for the following convolutional codes:
     16 
     17 r=1/2 k=7 ("Voyager" code, now a widely used industry standard)
     18 r=1/2 k=9 (Used on the IS-95 CDMA forward link)
     19 r=1/6 k=15 ("Cassini" code, used by several NASA/JPL deep space missions)
     20 
     21 2. Reed-Solomon encoders and decoders for any user-specified code.
     22 
     23 3. Optimized encoder and decoder for the CCSDS-standard (255,223)
     24 Reed-Solomon code, with and without the CCSDS-standard "dual basis"
     25 symbol representation.
     26 
     27 4. Compute dot product between a 16-bit buffer and a set of 16-bit
     28 coefficients. This is the basic DSP primitive for digital filtering
     29 and correlation.
     30 
     31 4. Compute sum of squares of a buffer of 16-bit signed integers. This is
     32 useful in DSP for finding the total energy in a signal.
     33 
     34 5. Find peak value in a buffer of 16-bit signed integers, useful for
     35 scaling a signal to prevent overflow.
     36 
     37 SIMD SUPPORT
     38 
     39 This package automatically makes use of various SIMD (Single
     40 Instruction stream, Multiple Data stream) instruction sets, when
     41 available: MMX, SSE and SSE2 on the IA-32 (Intel) architecture, and
     42 Altivec on the PowerPC G4 and G5 used by Power Macintoshes.
     43 
     44 "Altivec" is a Motorola trademark; Apple calls it "Velocity Engine",
     45 and IBM calls it "VMX". Altivec is roughly comparable to SSE2 on the
     46 IA-32.
     47 
     48 Many of the SIMD versions run more than an order of
     49 magnitude faster than their portable C versions. The available SIMD
     50 instruction sets, if any, are determined at run time and the proper
     51 version of each routine is automatically selected. If no SIMD
     52 instructions are available, the portable C version is invoked by
     53 default. On targets other than IA-32 and PPC, only the portable C
     54 version is built.
     55 
     56 The SIMD-assisted versions generally produce the same results as the C
     57 versions, with a few minor exceptions. The Viterbi decoders in C have
     58 a very slightly greater Eb/No performance due to their use of 32-bit
     59 path metrics. On the other hand, the SIMD versions use the
     60 "saturating" arithmetic available in these instructions to avoid the
     61 integer wraparounds that can occur in C when argument ranges are not
     62 properly constrained. This applies primarily to the "dotprod" (dot
     63 product) function.
     64 
     65 The MMX (MultiMedia eXtensions) instruction set was introduced on
     66 later Pentium CPUs; it is also implemented on the Pentium II and most
     67 AMD CPUs starting with the K6. SSE (SIMD Streaming Extensions) was
     68 introduced in the Pentium III; AMD calls it "3D Now! Professional".
     69 Intel introduced SSE2 on the Pentium 4, and it has been picked up by
     70 later AMD CPUs. SSE support implies MMX support, while SSE2 support
     71 implies both SSE and MMX support.
     72 
     73 The latest IA-32 SIMD instruction set, SSE3 (also known as "Prescott
     74 New Instructions") was introduced in early 2004 with the latest
     75 ("Prescott") revision of the Pentium 4. Relatively little was
     76 introduced with SSE3, and this library currently makes no use of it.
     77 
     78 See the various manual pages for details on how to use the library
     79 routines.
     80 
     81 Copyright 2006, Phil Karn, KA9Q
     82 karn (a] ka9q.net
     83 http://www.ka9q.net/
     84 
     85 This software may be used under the terms of the GNU Lesser General
     86 Public License (LGPL); see the file lesser.txt for details.
     87 
     88 Revision history:
     89 Version 1.0 released 29 May 2001
     90 
     91 Version 2.0 released 3 Dec 2001:
     92 Restructured to add support for shared libraries.
     93 
     94 Version 2.0.1 released 8 Dec 2001:
     95 Includes autoconf/configure script
     96 
     97 Version 2.0.2 released 4 Feb 2002:
     98 Add SIMD version override options
     99 Test for lack of SSE2 mnemonic support in 'as'
    100 Build only selected version
    101 
    102 Version 2.0.3 released 6 Feb 2002:
    103 Fix to parityb function in parity.h
    104 
    105 feclib version 1.0 released November 2003
    106 Merged SIMD-Viterbi, RS and DSP libraries
    107 Changed SIMD Viterbi decoder to detect SSE2/SSE/MMX at runtime rather than build time
    108 
    109 feclib version 2.0 (unreleased) Mar 2004
    110 General speedups and cleanups
    111 Switch from 4 to 8-bit input symbols on all Viterbi decoders
    112 Support for Altivec on PowerPC
    113 Support for k=15 r=1/6 Cassini/Mars Pathfinder/Mars Exploration Rover/STEREO code
    114 Changed license to GNU Lesser General Public License (LGPL)
    115 
    116 feclib version 2.1 June 5 2006
    117 Added error checking, fixed alignment bug in SSE2 versions of Viterbi decoders causing segfaults
    118 
    119 feclib version 2.1.1 June 6 2006
    120 Fix test/benchmark time measurement on Linux
    121