1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 /*! 21 ************************************************************************** 22 * \file ih264d_utils.c 23 * 24 * \brief 25 * Contains routines that handle of start and end of pic processing 26 * 27 * \date 28 * 19/12/2002 29 * 30 * \author AI 31 ************************************************************************** 32 */ 33 34 #include <string.h> 35 #include "ih264_typedefs.h" 36 #include "ithread.h" 37 #include "ih264d_deblocking.h" 38 #include "ih264d_parse_slice.h" 39 #include "ih264d_parse_cavlc.h" 40 #include "ih264d_dpb_manager.h" 41 #include "ih264d_defs.h" 42 #include "ih264d_structs.h" 43 #include "ih264d_mem_request.h" 44 #include "ih264_typedefs.h" 45 #include "ih264_macros.h" 46 #include "ih264_platform_macros.h" 47 #include "ih264d_tables.h" 48 #include "ih264d_debug.h" 49 #include "ih264d_mb_utils.h" 50 #include "ih264d_error_handler.h" 51 #include "ih264d_dpb_manager.h" 52 #include "ih264d_utils.h" 53 #include "ih264d_defs.h" 54 #include "ih264d_tables.h" 55 #include "ih264d_inter_pred.h" 56 #include "ih264d_dpb_manager.h" 57 #include "iv.h" 58 #include "ivd.h" 59 #include "ih264d_format_conv.h" 60 #include "ih264_error.h" 61 #include "ih264_disp_mgr.h" 62 #include "ih264_buf_mgr.h" 63 #include "ih264d_utils.h" 64 65 /*! 66 ************************************************************************** 67 * \if Function name : ih264d_is_end_of_pic \endif 68 * 69 * \brief 70 * Determines whether current slice is first slice of a new picture as 71 * defined in 7.4.1.2.4 of 14496-10. 72 * 73 * \return 74 * Return 1 if current slice is first slice of a new picture 75 * Otherwise it returns 0 76 ************************************************************************** 77 */ 78 UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num, 79 UWORD8 u1_nal_ref_idc, 80 pocstruct_t *ps_cur_poc, 81 pocstruct_t *ps_prev_poc, 82 dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/ 83 UWORD8 u1_pic_order_cnt_type, 84 UWORD8 u1_nal_unit_type, 85 UWORD32 u4_idr_pic_id, 86 UWORD8 u1_field_pic_flag, 87 UWORD8 u1_bottom_field_flag) 88 { 89 WORD8 i1_is_end_of_pic; 90 WORD8 a, b, c, d, e, f, g, h; 91 92 a = b = c = d = e = f = g = h = 0; 93 a = (ps_prev_slice->u2_frame_num != u2_frame_num); 94 b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag); 95 if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag) 96 c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag); 97 d = 98 (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0) 99 || (u1_nal_ref_idc != 0 100 && ps_prev_slice->u1_nal_ref_idc 101 == 0); 102 if(!a) 103 { 104 if((u1_pic_order_cnt_type == 0) 105 && (ps_prev_slice->u1_pic_order_cnt_type == 0)) 106 { 107 e = 108 ((ps_cur_poc->i4_pic_order_cnt_lsb 109 != ps_prev_poc->i4_pic_order_cnt_lsb) 110 || (ps_cur_poc->i4_delta_pic_order_cnt_bottom 111 != ps_prev_poc->i4_delta_pic_order_cnt_bottom)); 112 } 113 114 if((u1_pic_order_cnt_type == 1) 115 && (ps_prev_slice->u1_pic_order_cnt_type == 1)) 116 { 117 f = 118 ((ps_cur_poc->i4_delta_pic_order_cnt[0] 119 != ps_prev_poc->i4_delta_pic_order_cnt[0]) 120 || (ps_cur_poc->i4_delta_pic_order_cnt[1] 121 != ps_prev_poc->i4_delta_pic_order_cnt[1])); 122 } 123 } 124 125 if((u1_nal_unit_type == IDR_SLICE_NAL) 126 && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL)) 127 { 128 g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id); 129 } 130 131 if((u1_nal_unit_type == IDR_SLICE_NAL) 132 && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL)) 133 { 134 h = 1; 135 } 136 i1_is_end_of_pic = a + b + c + d + e + f + g + h; 137 return (i1_is_end_of_pic); 138 } 139 140 /*! 141 ************************************************************************** 142 * \if Function name : ih264d_decode_pic_order_cnt \endif 143 * 144 * \brief 145 * Calculates picture order count of picture. 146 * 147 * \return 148 * Returns the pic order count of the picture to which current 149 * Slice belongs. 150 * 151 ************************************************************************** 152 */ 153 WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice, 154 UWORD32 u2_frame_num, 155 pocstruct_t *ps_prev_poc, 156 pocstruct_t *ps_cur_poc, 157 dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/ 158 dec_pic_params_t * ps_pps, 159 UWORD8 u1_nal_ref_idc, 160 UWORD8 u1_bottom_field_flag, 161 UWORD8 u1_field_pic_flag, 162 WORD32 *pi4_poc) 163 { 164 WORD16 i1_pic_msb; 165 WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0; 166 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 167 WORD32 i4_prev_frame_num_ofst; 168 169 switch(ps_seq->u1_pic_order_cnt_type) 170 { 171 case 0: 172 /* POC TYPE 0 */ 173 if(u1_is_idr_slice) 174 { 175 ps_prev_poc->i4_pic_order_cnt_msb = 0; 176 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 177 } 178 if(ps_prev_poc->u1_mmco_equalto5) 179 { 180 if(ps_prev_poc->u1_bot_field != 1) 181 { 182 ps_prev_poc->i4_pic_order_cnt_msb = 0; 183 ps_prev_poc->i4_pic_order_cnt_lsb = 184 ps_prev_poc->i4_top_field_order_count; 185 } 186 else 187 { 188 ps_prev_poc->i4_pic_order_cnt_msb = 0; 189 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 190 } 191 } 192 193 if((ps_cur_poc->i4_pic_order_cnt_lsb 194 < ps_prev_poc->i4_pic_order_cnt_lsb) 195 && ((ps_prev_poc->i4_pic_order_cnt_lsb 196 - ps_cur_poc->i4_pic_order_cnt_lsb) 197 >= (ps_seq->i4_max_pic_order_cntLsb 198 >> 1))) 199 { 200 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 201 + ps_seq->i4_max_pic_order_cntLsb; 202 } 203 else if((ps_cur_poc->i4_pic_order_cnt_lsb 204 > ps_prev_poc->i4_pic_order_cnt_lsb) 205 && ((ps_cur_poc->i4_pic_order_cnt_lsb 206 - ps_prev_poc->i4_pic_order_cnt_lsb) 207 >= (ps_seq->i4_max_pic_order_cntLsb 208 >> 1))) 209 { 210 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 211 - ps_seq->i4_max_pic_order_cntLsb; 212 } 213 else 214 { 215 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb; 216 } 217 218 if(!u1_field_pic_flag || !u1_bottom_field_flag) 219 i4_top_field_order_cnt = i1_pic_msb 220 + ps_cur_poc->i4_pic_order_cnt_lsb; 221 222 if(!u1_field_pic_flag) 223 { 224 i4_bottom_field_order_cnt = i4_top_field_order_cnt 225 + ps_cur_poc->i4_delta_pic_order_cnt_bottom; 226 } 227 else if(u1_bottom_field_flag) 228 { 229 i4_bottom_field_order_cnt = i1_pic_msb 230 + ps_cur_poc->i4_pic_order_cnt_lsb; 231 } 232 ps_cur_poc->i4_pic_order_cnt_msb = i1_pic_msb; 233 break; 234 235 case 1: 236 { 237 /* POC TYPE 1 */ 238 UWORD8 i; 239 WORD32 prev_frame_num; 240 WORD32 frame_num_ofst; 241 WORD32 abs_frm_num; 242 WORD32 poc_cycle_cnt, frame_num_in_poc_cycle; 243 WORD32 expected_delta_poc_cycle; 244 WORD32 expected_poc; 245 246 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 247 if(!u1_is_idr_slice) 248 { 249 if(ps_cur_slice->u1_mmco_equalto5) 250 { 251 prev_frame_num = 0; 252 i4_prev_frame_num_ofst = 0; 253 } 254 else 255 { 256 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 257 } 258 } 259 else 260 i4_prev_frame_num_ofst = 0; 261 262 /* 1. Derivation for FrameNumOffset */ 263 if(u1_is_idr_slice) 264 { 265 frame_num_ofst = 0; 266 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 267 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 268 } 269 else if(prev_frame_num > ((WORD32)u2_frame_num)) 270 { 271 frame_num_ofst = i4_prev_frame_num_ofst 272 + ps_seq->u2_u4_max_pic_num_minus1 + 1; 273 } 274 else 275 frame_num_ofst = i4_prev_frame_num_ofst; 276 277 /* 2. Derivation for absFrameNum */ 278 if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle) 279 abs_frm_num = frame_num_ofst + u2_frame_num; 280 else 281 abs_frm_num = 0; 282 if((u1_nal_ref_idc == 0) && (abs_frm_num > 0)) 283 abs_frm_num = abs_frm_num - 1; 284 285 /* 4. expectedDeltaPerPicOrderCntCycle is derived as */ 286 expected_delta_poc_cycle = 0; 287 for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle; 288 i++) 289 { 290 expected_delta_poc_cycle += 291 ps_seq->i4_ofst_for_ref_frame[i]; 292 } 293 294 /* 3. When absFrameNum > 0, picOrderCntCycleCnt and 295 frame_num_in_poc_cycle are derived as : */ 296 /* 5. expectedPicOrderCnt is derived as : */ 297 if(abs_frm_num > 0) 298 { 299 poc_cycle_cnt = 300 DIV((abs_frm_num - 1), 301 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 302 frame_num_in_poc_cycle = 303 MOD((abs_frm_num - 1), 304 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 305 306 expected_poc = poc_cycle_cnt 307 * expected_delta_poc_cycle; 308 for(i = 0; i <= frame_num_in_poc_cycle; i++) 309 { 310 expected_poc = expected_poc 311 + ps_seq->i4_ofst_for_ref_frame[i]; 312 } 313 } 314 else 315 expected_poc = 0; 316 317 if(u1_nal_ref_idc == 0) 318 { 319 expected_poc = expected_poc 320 + ps_seq->i4_ofst_for_non_ref_pic; 321 } 322 323 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 324 if(!u1_field_pic_flag) 325 { 326 i4_top_field_order_cnt = expected_poc 327 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 328 i4_bottom_field_order_cnt = i4_top_field_order_cnt 329 + ps_seq->i4_ofst_for_top_to_bottom_field 330 + ps_cur_poc->i4_delta_pic_order_cnt[1]; 331 } 332 else if(!u1_bottom_field_flag) 333 { 334 i4_top_field_order_cnt = expected_poc 335 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 336 } 337 else 338 { 339 i4_bottom_field_order_cnt = expected_poc 340 + ps_seq->i4_ofst_for_top_to_bottom_field 341 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 342 } 343 /* Copy the current POC info into Previous POC structure */ 344 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 345 } 346 347 break; 348 case 2: 349 { 350 /* POC TYPE 2 */ 351 WORD32 prev_frame_num; 352 WORD32 frame_num_ofst; 353 WORD32 tmp_poc; 354 355 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 356 if(!u1_is_idr_slice) 357 { 358 if(ps_cur_slice->u1_mmco_equalto5) 359 { 360 prev_frame_num = 0; 361 i4_prev_frame_num_ofst = 0; 362 } 363 else 364 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 365 } 366 else 367 i4_prev_frame_num_ofst = 0; 368 369 /* 1. Derivation for FrameNumOffset */ 370 if(u1_is_idr_slice) 371 { 372 frame_num_ofst = 0; 373 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 374 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 375 } 376 else if(prev_frame_num > ((WORD32)u2_frame_num)) 377 { 378 frame_num_ofst = i4_prev_frame_num_ofst 379 + ps_seq->u2_u4_max_pic_num_minus1 + 1; 380 } 381 else 382 frame_num_ofst = i4_prev_frame_num_ofst; 383 384 /* 2. Derivation for tempPicOrderCnt */ 385 if(u1_is_idr_slice) 386 tmp_poc = 0; 387 else if(u1_nal_ref_idc == 0) 388 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1) 389 - 1; 390 else 391 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1); 392 393 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 394 if(!u1_field_pic_flag) 395 { 396 i4_top_field_order_cnt = tmp_poc; 397 i4_bottom_field_order_cnt = tmp_poc; 398 } 399 else if(!u1_bottom_field_flag) 400 i4_top_field_order_cnt = tmp_poc; 401 else 402 i4_bottom_field_order_cnt = tmp_poc; 403 404 /* Copy the current POC info into Previous POC structure */ 405 ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst; 406 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 407 } 408 break; 409 default: 410 return ERROR_INV_POC_TYPE_T; 411 break; 412 } 413 414 if(!u1_field_pic_flag) // or a complementary field pair 415 { 416 *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt); 417 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 418 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 419 } 420 else if(!u1_bottom_field_flag) 421 { 422 *pi4_poc = i4_top_field_order_cnt; 423 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 424 } 425 else 426 { 427 *pi4_poc = i4_bottom_field_order_cnt; 428 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 429 } 430 431 ps_pps->i4_avg_poc = *pi4_poc; 432 433 return OK; 434 } 435 436 /*! 437 ************************************************************************** 438 * \if Function name : ih264d_end_of_pic_processing \endif 439 * 440 * \brief 441 * Performs the end of picture processing. 442 * 443 * It performs deblocking on the current picture and sets the i4_status of 444 * current picture as decoded. 445 * 446 * \return 447 * 0 on Success and Error code otherwise. 448 ************************************************************************** 449 */ 450 WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec) 451 { 452 UWORD8 u1_pic_type, u1_nal_ref_idc; 453 dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice; 454 455 /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL 456 unit of a particular picture, it shall be equal to 0 for all slice and 457 slice data partition NAL units of the picture. nal_ref_idc greater 458 than 0 indicates that the content of the NAL unit belongs to a decoded 459 picture that is stored and marked for use as a reference picture in the 460 decoded picture buffer. */ 461 462 /* 1. Do MMCO 463 2. Add Cur Pic to list of reference pics. 464 */ 465 466 /* Call MMCO */ 467 u1_pic_type = 0; 468 u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc; 469 470 if(u1_nal_ref_idc) 471 { 472 if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 473 { 474 if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0) 475 { 476 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 477 /* ignore DPB errors */ 478 ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 479 ps_dec->ps_cur_pic, 480 ps_dec->u1_pic_buf_id, 481 ps_cur_slice->u2_frame_num); 482 } 483 else 484 { 485 /* Equivalent of inserting a pic directly as longterm Pic */ 486 487 { 488 /* ignore DPB errors */ 489 ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 490 ps_dec->ps_cur_pic, 491 ps_dec->u1_pic_buf_id, 492 ps_cur_slice->u2_frame_num); 493 494 /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */ 495 ih264d_delete_st_node_or_make_lt( 496 ps_dec->ps_dpb_mgr, 497 ps_cur_slice->u2_frame_num, 0, 498 ps_cur_slice->u1_field_pic_flag); 499 500 ps_dec->ps_dpb_mgr->u1_max_lt_pic_idx_plus1 = 1; 501 } 502 } 503 } 504 else 505 { 506 507 { 508 UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num; 509 510 /* ignore DPB errors */ 511 ih264d_do_mmco_buffer(ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr, 512 ps_dec->ps_cur_sps->u1_num_ref_frames, u2_pic_num, 513 (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1), 514 ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic, 515 ps_dec->u1_pic_buf_id, 516 ps_cur_slice->u1_field_pic_flag, 517 ps_dec->e_dec_status); 518 519 520 } 521 } 522 ih264d_update_default_index_list(ps_dec->ps_dpb_mgr); 523 } 524 525 if(ps_cur_slice->u1_field_pic_flag) 526 { 527 if(ps_cur_slice->u1_bottom_field_flag) 528 { 529 if(u1_nal_ref_idc) 530 u1_pic_type = u1_pic_type | BOT_REF; 531 u1_pic_type = u1_pic_type | BOT_FLD; 532 } 533 else 534 { 535 if(u1_nal_ref_idc) 536 u1_pic_type = u1_pic_type | TOP_REF; 537 u1_pic_type = u1_pic_type | TOP_FLD; 538 } 539 } 540 else 541 u1_pic_type = TOP_REF | BOT_REF; 542 ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type; 543 544 545 if(ps_cur_slice->u1_field_pic_flag) 546 { 547 H264_DEC_DEBUG_PRINT("Toggling secondField\n"); 548 ps_dec->u1_second_field = 1 - ps_dec->u1_second_field; 549 } 550 551 return OK; 552 } 553 554 /*****************************************************************************/ 555 /* */ 556 /* Function Name : init_dpb_size */ 557 /* */ 558 /* Description : This function calculates the DBP i4_size in frames */ 559 /* Inputs : ps_seq - current sequence params */ 560 /* */ 561 /* Globals : None */ 562 /* */ 563 /* Outputs : None */ 564 /* */ 565 /* Returns : DPB in frames */ 566 /* */ 567 /* Issues : None */ 568 /* */ 569 /* Revision History: */ 570 /* */ 571 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 572 /* 28 04 2005 NS Draft */ 573 /* */ 574 /*****************************************************************************/ 575 WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq) 576 { 577 WORD32 i4_size; 578 UWORD8 u1_level_idc; 579 580 u1_level_idc = ps_seq->u1_level_idc; 581 582 switch(u1_level_idc) 583 { 584 case 10: 585 i4_size = 152064; 586 break; 587 case 11: 588 i4_size = 345600; 589 break; 590 case 12: 591 i4_size = 912384; 592 break; 593 case 13: 594 i4_size = 912384; 595 break; 596 case 20: 597 i4_size = 912384; 598 break; 599 case 21: 600 i4_size = 1824768; 601 break; 602 case 22: 603 i4_size = 3110400; 604 break; 605 case 30: 606 i4_size = 3110400; 607 break; 608 case 31: 609 i4_size = 6912000; 610 break; 611 case 32: 612 i4_size = 7864320; 613 break; 614 case 40: 615 i4_size = 12582912; 616 break; 617 case 41: 618 i4_size = 12582912; 619 break; 620 case 42: 621 i4_size = 12582912; 622 break; 623 case 50: 624 i4_size = 42393600; 625 break; 626 case 51: 627 i4_size = 70778880; 628 break; 629 case 52: 630 i4_size = 70778880; 631 break; 632 default: 633 i4_size = 70778880; 634 break; 635 } 636 637 i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag))); 638 i4_size /= 384; 639 i4_size = MIN(i4_size, 16); 640 i4_size = MAX(i4_size, 1); 641 return (i4_size); 642 } 643 644 /**************************************************************************/ 645 /* This function initialises the value of ps_dec->u1_recon_mb_grp */ 646 /* ps_dec->u1_recon_mb_grp must satisfy the following criteria */ 647 /* - multiple of 2 (required for N/2 parse-mvpred design) */ 648 /* - multiple of 4 (if it is not a frame_mbs_only sequence), */ 649 /* in this case N/2 itself needs to be even for mbpair processing */ 650 /* - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks */ 651 /* should make a row to ensure proper MvTop transferring) */ 652 /**************************************************************************/ 653 WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec) 654 { 655 dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps; 656 UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag; 657 658 ps_dec->u1_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs << ps_seq->u1_mb_aff_flag; 659 660 ps_dec->u1_recon_mb_grp_pair = ps_dec->u1_recon_mb_grp >> 1; 661 662 if(!ps_dec->u1_recon_mb_grp) 663 { 664 return ERROR_MB_GROUP_ASSGN_T; 665 } 666 667 ps_dec->u4_num_mbs_prev_nmb = ps_dec->u1_recon_mb_grp; 668 669 return OK; 670 } 671 672 673 /*! 674 ************************************************************************** 675 * \if Function name : ih264d_init_pic \endif 676 * 677 * \brief 678 * Initializes the picture. 679 * 680 * \return 681 * 0 on Success and Error code otherwise 682 * 683 * \note 684 * This function is called when first slice of the 685 * NON -IDR picture is encountered. 686 ************************************************************************** 687 */ 688 WORD32 ih264d_init_pic(dec_struct_t *ps_dec, 689 UWORD16 u2_frame_num, 690 WORD32 i4_poc, 691 dec_pic_params_t *ps_pps) 692 { 693 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 694 prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params; 695 WORD32 i4_pic_bufs; 696 WORD32 ret; 697 698 ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num; 699 ps_dec->ps_cur_slice->i4_poc = i4_poc; 700 ps_dec->ps_cur_pps = ps_pps; 701 ps_dec->ps_cur_pps->pv_codec_handle = ps_dec; 702 703 ps_dec->ps_cur_sps = ps_seq; 704 ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1 705 + 1; 706 707 ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht; 708 ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd; 709 ps_dec->i4_pic_type = -1; 710 ps_dec->i4_frametype = -1; 711 ps_dec->i4_content_type = -1; 712 713 /*--------------------------------------------------------------------*/ 714 /* Get the value of MaxMbAddress and frmheight in Mbs */ 715 /*--------------------------------------------------------------------*/ 716 ps_seq->u2_max_mb_addr = 717 (ps_seq->u2_frm_wd_in_mbs 718 * (ps_dec->u2_pic_ht 719 >> (4 720 + ps_dec->ps_cur_slice->u1_field_pic_flag))) 721 - 1; 722 ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht 723 >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag)); 724 725 /***************************************************************************/ 726 /* If change in Level or the required PicBuffers i4_size is more than the */ 727 /* current one FREE the current PicBuffers and allocate affresh */ 728 /***************************************************************************/ 729 if(!ps_dec->u1_init_dec_flag) 730 { 731 ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq); 732 733 ps_dec->i4_display_delay = ps_dec->u1_max_dec_frame_buffering; 734 if((1 == ps_seq->u1_vui_parameters_present_flag) && 735 (1 == ps_seq->s_vui.u1_bitstream_restriction_flag)) 736 { 737 if(ps_seq->u1_frame_mbs_only_flag == 1) 738 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames + 1; 739 else 740 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames * 2 + 2; 741 } 742 743 if(IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode) 744 ps_dec->i4_display_delay = 0; 745 746 if(ps_dec->u4_share_disp_buf == 0) 747 { 748 if(ps_seq->u1_frame_mbs_only_flag == 1) 749 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames + 1; 750 else 751 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames * 2 + 2; 752 } 753 else 754 { 755 ps_dec->u1_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs; 756 } 757 758 /* Ensure at least two buffers are allocated */ 759 ps_dec->u1_pic_bufs = MAX(ps_dec->u1_pic_bufs, 2); 760 761 if(ps_dec->u4_share_disp_buf == 0) 762 ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs, 763 (H264_MAX_REF_PICS * 2)); 764 765 ps_dec->u1_max_dec_frame_buffering = MIN( 766 ps_dec->u1_max_dec_frame_buffering, 767 ps_dec->u1_pic_bufs); 768 769 /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams also for CAFI1_SVA_C.264 in conformance*/ 770 if(ps_dec->u1_init_dec_flag) 771 { 772 ih264d_release_pics_in_dpb((void *)ps_dec, 773 ps_dec->u1_pic_bufs); 774 ih264d_release_display_bufs(ps_dec); 775 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 776 } 777 778 /*********************************************************************/ 779 /* Configuring decoder parameters based on level and then */ 780 /* fresh pointer initialisation in decoder scratch and state buffers */ 781 /*********************************************************************/ 782 if(!ps_dec->u1_init_dec_flag || 783 ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0))) 784 { 785 ret = ih264d_init_dec_mb_grp(ps_dec); 786 if(ret != OK) 787 return ret; 788 } 789 790 ret = ih264d_allocate_dynamic_bufs(ps_dec); 791 if(ret != OK) 792 { 793 /* Free any dynamic buffers that are allocated */ 794 ih264d_free_dynamic_bufs(ps_dec); 795 ps_dec->i4_error_code = IVD_MEM_ALLOC_FAILED; 796 return IVD_MEM_ALLOC_FAILED; 797 } 798 799 ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs, 800 ps_dec); 801 if(ret != OK) 802 return ret; 803 804 805 806 ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd, 807 ps_dec->u2_pic_ht); 808 if(ret != OK) 809 return ret; 810 811 /* In shared mode, set all of them as used by display */ 812 if(ps_dec->u4_share_disp_buf == 1) 813 { 814 WORD32 i; 815 816 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 817 { 818 ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 819 BUF_MGR_IO); 820 } 821 } 822 823 ps_dec->u1_init_dec_flag = 1; 824 ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs; 825 ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc; 826 ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc; 827 ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs; 828 ps_prev_seq_params->u1_frame_mbs_only_flag = 829 ps_seq->u1_frame_mbs_only_flag; 830 ps_prev_seq_params->u1_direct_8x8_inference_flag = 831 ps_seq->u1_direct_8x8_inference_flag; 832 833 ps_dec->i4_cur_display_seq = 0; 834 ps_dec->i4_prev_max_display_seq = 0; 835 ps_dec->i4_max_poc = 0; 836 837 { 838 /* 0th entry of CtxtIncMbMap will be always be containing default values 839 for CABAC context representing MB not available */ 840 ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1; 841 UWORD8 *pu1_temp; 842 WORD8 i; 843 p_DefCtxt->u1_mb_type = CAB_SKIP; 844 845 p_DefCtxt->u1_cbp = 0x0f; 846 p_DefCtxt->u1_intra_chroma_pred_mode = 0; 847 848 p_DefCtxt->u1_yuv_dc_csbp = 0x7; 849 850 p_DefCtxt->u1_transform8x8_ctxt = 0; 851 852 pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx; 853 for(i = 0; i < 4; i++, pu1_temp++) 854 (*pu1_temp) = 0; 855 pu1_temp = (UWORD8*)p_DefCtxt->u1_mv; 856 for(i = 0; i < 16; i++, pu1_temp++) 857 (*pu1_temp) = 0; 858 ps_dec->ps_def_ctxt_mb_info = p_DefCtxt; 859 } 860 861 } 862 /* reset DBP commands read u4_flag */ 863 ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0; 864 865 return OK; 866 } 867 868 /*****************************************************************************/ 869 /* */ 870 /* Function Name : ih264d_get_next_display_field */ 871 /* */ 872 /* Description : Application calls this module to get the next field */ 873 /* to be displayed */ 874 /* */ 875 /* Inputs : 1. IBUFAPI_Handle Hnadle to the Display buffer */ 876 /* 2. IH264DEC_DispUnit Pointer to the display struct */ 877 /* */ 878 /* Globals : */ 879 /* */ 880 /* */ 881 /* Processing : None */ 882 /* Outputs : None */ 883 /* Returns : None */ 884 /* Issues : None */ 885 /* */ 886 /* Revision History: */ 887 /* */ 888 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 889 /* 27 05 2005 Ittiam Draft */ 890 /* */ 891 /*****************************************************************************/ 892 893 WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec, 894 ivd_out_bufdesc_t *ps_out_buffer, 895 ivd_get_display_frame_op_t *pv_disp_op) 896 { 897 pic_buffer_t *pic_buf; 898 899 UWORD8 i1_cur_fld; 900 WORD32 u4_api_ret = -1; 901 WORD32 i4_disp_buf_id; 902 iv_yuv_buf_t *ps_op_frm; 903 904 905 906 ps_op_frm = &(ps_dec->s_disp_frame_info); 907 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 908 pic_buf = (pic_buffer_t *)ih264_disp_mgr_get( 909 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id); 910 ps_dec->u4_num_fld_in_frm = 0; 911 u4_api_ret = -1; 912 pv_disp_op->u4_ts = -1; 913 pv_disp_op->e_output_format = ps_dec->u1_chroma_format; 914 915 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0]; 916 pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1]; 917 pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2]; 918 if(pic_buf != NULL) 919 { 920 pv_disp_op->e4_fld_type = 0; 921 pv_disp_op->u4_disp_buf_id = i4_disp_buf_id; 922 923 ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1; 924 ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1; 925 ps_op_frm->u4_y_wd = pic_buf->u2_disp_width; 926 927 ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1; 928 929 ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y; 930 ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv; 931 932 /* ! */ 933 pv_disp_op->u4_ts = pic_buf->u4_ts; 934 935 /* set the start of the Y, U and V buffer pointer for display */ 936 ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y; 937 ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv; 938 ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv; 939 ps_dec->u4_num_fld_in_frm++; 940 ps_dec->u4_num_fld_in_frm++; 941 u4_api_ret = 0; 942 943 if(pic_buf->u1_picturetype == 0) 944 pv_disp_op->u4_progressive_frame_flag = 1; 945 else 946 pv_disp_op->u4_progressive_frame_flag = 0; 947 948 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 949 pv_disp_op->u4_error_code = u4_api_ret; 950 pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk; 951 952 if(u4_api_ret) 953 { 954 pv_disp_op->u4_error_code = 1; //put a proper error code here 955 } 956 else 957 { 958 959 //Release the buffer if being sent for display 960 UWORD32 temp; 961 UWORD32 dest_inc_Y = 0, dest_inc_UV = 0; 962 963 pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd, 964 ps_op_frm->u4_y_strd); 965 pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 966 >> 1; 967 pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 968 >> 1; 969 970 pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht; 971 pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 972 >> 1; 973 pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 974 >> 1; 975 if(0 == ps_dec->u4_share_disp_buf) 976 { 977 pv_disp_op->s_disp_frm_buf.u4_y_strd = 978 pv_disp_op->s_disp_frm_buf.u4_y_wd; 979 pv_disp_op->s_disp_frm_buf.u4_u_strd = 980 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 981 pv_disp_op->s_disp_frm_buf.u4_v_strd = 982 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 983 984 } 985 else 986 { 987 pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd; 988 } 989 990 if(ps_dec->u4_app_disp_width) 991 { 992 pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX( 993 ps_dec->u4_app_disp_width, 994 pv_disp_op->s_disp_frm_buf.u4_y_strd); 995 } 996 997 pv_disp_op->u4_error_code = 0; 998 if(pv_disp_op->e_output_format == IV_YUV_420P) 999 { 1000 UWORD32 i; 1001 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1002 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1003 pv_disp_op->s_disp_frm_buf.u4_v_strd = 1004 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1005 1006 pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1; 1007 pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1; 1008 1009 if(1 == ps_dec->u4_share_disp_buf) 1010 { 1011 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1012 1013 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1014 { 1015 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1016 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1017 if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1018 - pic_buf->u2_crop_offset_y) == buf) 1019 { 1020 buf = ps_dec->disp_bufs[i].buf[1]; 1021 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1022 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1023 + pic_buf->u2_crop_offset_uv; 1024 1025 buf = ps_dec->disp_bufs[i].buf[2]; 1026 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1027 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1028 + pic_buf->u2_crop_offset_uv; 1029 } 1030 } 1031 } 1032 1033 } 1034 else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV) 1035 || (pv_disp_op->e_output_format == IV_YUV_420SP_VU)) 1036 { 1037 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1038 pv_disp_op->s_disp_frm_buf.u4_y_strd; 1039 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1040 1041 if(1 == ps_dec->u4_share_disp_buf) 1042 { 1043 UWORD32 i; 1044 1045 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1046 1047 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1048 { 1049 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1050 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1051 if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1052 - pic_buf->u2_crop_offset_y == buf) 1053 { 1054 buf = ps_dec->disp_bufs[i].buf[1]; 1055 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1056 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1057 + pic_buf->u2_crop_offset_uv; 1058 ; 1059 1060 buf = ps_dec->disp_bufs[i].buf[2]; 1061 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1062 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1063 + pic_buf->u2_crop_offset_uv; 1064 ; 1065 } 1066 } 1067 } 1068 pv_disp_op->s_disp_frm_buf.u4_u_wd = 1069 pv_disp_op->s_disp_frm_buf.u4_y_wd; 1070 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1071 1072 } 1073 else if((pv_disp_op->e_output_format == IV_RGB_565) 1074 || (pv_disp_op->e_output_format == IV_YUV_422ILE)) 1075 { 1076 1077 pv_disp_op->s_disp_frm_buf.u4_u_strd = 0; 1078 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1079 pv_disp_op->s_disp_frm_buf.u4_u_wd = 0; 1080 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1081 pv_disp_op->s_disp_frm_buf.u4_u_ht = 0; 1082 pv_disp_op->s_disp_frm_buf.u4_v_ht = 0; 1083 1084 } 1085 1086 1087 } 1088 1089 return u4_api_ret; 1090 } 1091 1092 1093 /*****************************************************************************/ 1094 /* Function Name : ih264d_release_display_field */ 1095 /* */ 1096 /* Description : This function releases the display field that was returned */ 1097 /* here. */ 1098 /* Inputs : ps_dec - Decoder parameters */ 1099 /* Globals : None */ 1100 /* Processing : Refer bumping process in the standard */ 1101 /* Outputs : Assigns display sequence number. */ 1102 /* Returns : None */ 1103 /* */ 1104 /* Issues : None */ 1105 /* */ 1106 /* Revision History: */ 1107 /* */ 1108 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1109 /* 27 04 2005 NS Draft */ 1110 /* */ 1111 /*****************************************************************************/ 1112 void ih264d_release_display_field(dec_struct_t *ps_dec, 1113 ivd_get_display_frame_op_t *pv_disp_op) 1114 { 1115 if(1 == pv_disp_op->u4_error_code) 1116 { 1117 if(1 == ps_dec->u1_flushfrm) 1118 { 1119 UWORD32 i; 1120 1121 if(1 == ps_dec->u4_share_disp_buf) 1122 { 1123 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1124 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1125 { 1126 if(1 == ps_dec->u4_disp_buf_mapping[i]) 1127 { 1128 ih264_buf_mgr_release( 1129 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 1130 BUF_MGR_IO); 1131 ps_dec->u4_disp_buf_mapping[i] = 0; 1132 } 1133 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1134 1135 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1136 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1137 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1138 ps_dec->u4_disp_buf_mapping[i] = 1; 1139 } 1140 ps_dec->u1_flushfrm = 0; 1141 1142 } 1143 } 1144 else 1145 { 1146 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1147 1148 if(0 == ps_dec->u4_share_disp_buf) 1149 { 1150 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1151 pv_disp_op->u4_disp_buf_id, 1152 BUF_MGR_IO); 1153 1154 } 1155 else 1156 { 1157 ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1; 1158 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1159 1160 } 1161 } 1162 /*****************************************************************************/ 1163 /* Function Name : ih264d_assign_display_seq */ 1164 /* */ 1165 /* Description : This function implments bumping process. Every outgoing */ 1166 /* frame from DPB is assigned a display sequence number */ 1167 /* which increases monotonically. System looks for this */ 1168 /* number to display a frame. */ 1169 /* here. */ 1170 /* Inputs : ps_dec - Decoder parameters */ 1171 /* Globals : None */ 1172 /* Processing : Refer bumping process in the standard */ 1173 /* Outputs : Assigns display sequence number. */ 1174 /* Returns : None */ 1175 /* */ 1176 /* Issues : None */ 1177 /* */ 1178 /* Revision History: */ 1179 /* */ 1180 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1181 /* 27 04 2005 NS Draft */ 1182 /* */ 1183 /*****************************************************************************/ 1184 WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec) 1185 { 1186 WORD32 i; 1187 WORD32 i4_min_poc; 1188 WORD32 i4_min_poc_buf_id; 1189 WORD32 i4_min_index; 1190 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1191 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1192 1193 i4_min_poc = 0x7fffffff; 1194 i4_min_poc_buf_id = -1; 1195 i4_min_index = -1; 1196 1197 if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay) 1198 { 1199 for(i = 0; i < MAX_FRAMES; i++) 1200 { 1201 if((i4_poc_buf_id_map[i][0] != -1) 1202 && (DO_NOT_DISP 1203 != ps_dpb_mgr->ai4_poc_buf_id_map[i][0])) 1204 { 1205 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1206 { 1207 i4_min_poc = i4_poc_buf_id_map[i][1]; 1208 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1209 i4_min_index = i; 1210 } 1211 } 1212 } 1213 1214 if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id)) 1215 { 1216 ps_dec->i4_cur_display_seq++; 1217 ih264_disp_mgr_add( 1218 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1219 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1220 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1221 i4_poc_buf_id_map[i4_min_index][0] = -1; 1222 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1223 ps_dpb_mgr->i1_poc_buf_id_entries--; 1224 } 1225 else if(DO_NOT_DISP == i4_min_poc_buf_id) 1226 { 1227 WORD32 i4_error_code; 1228 i4_error_code = ERROR_GAPS_IN_FRM_NUM; 1229 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1230 return i4_error_code; 1231 } 1232 } 1233 return OK; 1234 } 1235 1236 /*****************************************************************************/ 1237 /* */ 1238 /* Function Name : ih264d_release_display_bufs */ 1239 /* */ 1240 /* Description : This function implments bumping process when mmco = 5. */ 1241 /* Each outgoing frame from DPB is assigned a display */ 1242 /* sequence number which increases monotonically. System */ 1243 /* looks for this number to display a frame. */ 1244 /* Inputs : ps_dec - Decoder parameters */ 1245 /* Globals : None */ 1246 /* Processing : Refer bumping process in the standard for mmco = 5 */ 1247 /* Outputs : Assigns display sequence number. */ 1248 /* Returns : None */ 1249 /* */ 1250 /* Issues : None */ 1251 /* */ 1252 /* Revision History: */ 1253 /* */ 1254 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1255 /* 27 04 2005 NS Draft */ 1256 /* */ 1257 /*****************************************************************************/ 1258 void ih264d_release_display_bufs(dec_struct_t *ps_dec) 1259 { 1260 WORD32 i, j; 1261 WORD32 i4_min_poc; 1262 WORD32 i4_min_poc_buf_id; 1263 WORD32 i4_min_index; 1264 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1265 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1266 1267 i4_min_poc = 0x7fffffff; 1268 i4_min_poc_buf_id = -1; 1269 i4_min_index = -1; 1270 1271 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1272 1273 for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++) 1274 { 1275 i4_min_poc = 0x7fffffff; 1276 for(i = 0; i < MAX_FRAMES; i++) 1277 { 1278 if(i4_poc_buf_id_map[i][0] != -1) 1279 { 1280 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1281 { 1282 i4_min_poc = i4_poc_buf_id_map[i][1]; 1283 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1284 i4_min_index = i; 1285 } 1286 } 1287 } 1288 1289 if(DO_NOT_DISP != i4_min_poc_buf_id) 1290 { 1291 ps_dec->i4_cur_display_seq++; 1292 ih264_disp_mgr_add( 1293 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1294 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1295 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1296 i4_poc_buf_id_map[i4_min_index][0] = -1; 1297 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1298 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1299 } 1300 else 1301 { 1302 i4_poc_buf_id_map[i4_min_index][0] = -1; 1303 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1304 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1305 } 1306 } 1307 ps_dpb_mgr->i1_poc_buf_id_entries = 0; 1308 ps_dec->i4_prev_max_display_seq = ps_dec->i4_prev_max_display_seq 1309 + ps_dec->i4_max_poc + ps_dec->u1_max_dec_frame_buffering 1310 + 1; 1311 ps_dec->i4_max_poc = 0; 1312 } 1313 1314 /*****************************************************************************/ 1315 /* */ 1316 /* Function Name : ih264d_assign_pic_num */ 1317 /* */ 1318 /* Description : This function assigns pic num to each reference frame */ 1319 /* depending on the cur_frame_num as speified in section */ 1320 /* 8.2.4.1 */ 1321 /* */ 1322 /* Inputs : ps_dec */ 1323 /* */ 1324 /* Globals : NO globals used */ 1325 /* */ 1326 /* Processing : for all ST pictures */ 1327 /* if( FrameNum > cur_frame_num) */ 1328 /* PicNum = FrameNum - MaxFrameNum */ 1329 /* else */ 1330 /* PicNum = FrameNum */ 1331 /* */ 1332 /* Returns : void */ 1333 /* */ 1334 /* Issues : NO */ 1335 /* */ 1336 /* Revision History: */ 1337 /* */ 1338 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1339 /* 13 07 2002 Jay Draft */ 1340 /* */ 1341 /*****************************************************************************/ 1342 1343 void ih264d_assign_pic_num(dec_struct_t *ps_dec) 1344 { 1345 dpb_manager_t *ps_dpb_mgr; 1346 struct dpb_info_t *ps_next_dpb; 1347 WORD8 i; 1348 WORD32 i4_cur_frame_num, i4_max_frame_num; 1349 WORD32 i4_ref_frame_num; 1350 UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag; 1351 1352 i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1353 i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num; 1354 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1355 1356 /* Start from ST head */ 1357 ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head; 1358 for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++) 1359 { 1360 WORD32 i4_pic_num; 1361 1362 i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num; 1363 if(i4_ref_frame_num > i4_cur_frame_num) 1364 { 1365 /* RefPic Buf frame_num is before Current frame_num in decode order */ 1366 i4_pic_num = i4_ref_frame_num - i4_max_frame_num; 1367 } 1368 else 1369 { 1370 /* RefPic Buf frame_num is after Current frame_num in decode order */ 1371 i4_pic_num = i4_ref_frame_num; 1372 } 1373 1374 ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num; 1375 ps_next_dpb->i4_frame_num = i4_pic_num; 1376 ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1377 if(u1_fld_pic_flag) 1378 { 1379 /* Assign the pic num to top fields and bot fields */ 1380 1381 ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2 1382 + !(ps_dec->ps_cur_slice->u1_bottom_field_flag); 1383 ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2 1384 + ps_dec->ps_cur_slice->u1_bottom_field_flag; 1385 } 1386 /* Chase the next link */ 1387 ps_next_dpb = ps_next_dpb->ps_prev_short; 1388 } 1389 1390 if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag 1391 && ps_dpb_mgr->u1_num_gaps) 1392 { 1393 WORD32 i4_start_frm, i4_end_frm; 1394 /* Assign pic numbers for gaps */ 1395 for(i = 0; i < MAX_FRAMES; i++) 1396 { 1397 i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i]; 1398 if(i4_start_frm != INVALID_FRAME_NUM) 1399 { 1400 if(i4_start_frm > i4_cur_frame_num) 1401 { 1402 /* gap's frame_num is before Current frame_num in 1403 decode order */ 1404 i4_start_frm -= i4_max_frame_num; 1405 } 1406 ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm; 1407 i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i]; 1408 1409 if(i4_end_frm > i4_cur_frame_num) 1410 { 1411 /* gap's frame_num is before Current frame_num in 1412 decode order */ 1413 i4_end_frm -= i4_max_frame_num; 1414 } 1415 ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm; 1416 } 1417 } 1418 } 1419 } 1420 1421 /*! 1422 ************************************************************************** 1423 * \if Function name : ih264d_update_qp \endif 1424 * 1425 * \brief 1426 * Updates the values of QP and its related entities 1427 * 1428 * \return 1429 * 0 on Success and Error code otherwise 1430 * 1431 ************************************************************************** 1432 */ 1433 WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp) 1434 { 1435 WORD32 i_temp; 1436 i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52; 1437 1438 if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25)) 1439 return ERROR_INV_RANGE_QP_T; 1440 1441 ps_dec->u1_qp = i_temp; 1442 ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6; 1443 ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6; 1444 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset); 1445 ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1446 ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1447 1448 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset); 1449 ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1450 ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1451 1452 ps_dec->pu2_quant_scale_y = 1453 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6]; 1454 ps_dec->pu2_quant_scale_u = 1455 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6]; 1456 ps_dec->pu2_quant_scale_v = 1457 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6]; 1458 return OK; 1459 } 1460 1461 /*****************************************************************************/ 1462 /* */ 1463 /* Function Name : ih264d_decode_gaps_in_frame_num */ 1464 /* */ 1465 /* Description : This function decodes gaps in frame number */ 1466 /* */ 1467 /* Inputs : ps_dec Decoder parameters */ 1468 /* u2_frame_num current frame number */ 1469 /* */ 1470 /* Globals : None */ 1471 /* Processing : This functionality needs to be implemented */ 1472 /* Outputs : None */ 1473 /* Returns : None */ 1474 /* */ 1475 /* Issues : Not implemented */ 1476 /* */ 1477 /* Revision History: */ 1478 /* */ 1479 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1480 /* 06 05 2002 NS Draft */ 1481 /* */ 1482 /*****************************************************************************/ 1483 WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec, 1484 UWORD16 u2_frame_num) 1485 { 1486 UWORD32 u4_next_frm_num, u4_start_frm_num; 1487 UWORD32 u4_max_frm_num; 1488 pocstruct_t s_tmp_poc; 1489 WORD32 i4_poc; 1490 dec_slice_params_t *ps_cur_slice; 1491 1492 dec_pic_params_t *ps_pic_params; 1493 WORD8 i1_gap_idx; 1494 WORD32 *i4_gaps_start_frm_num; 1495 dpb_manager_t *ps_dpb_mgr; 1496 WORD32 i4_frame_gaps; 1497 WORD8 *pi1_gaps_per_seq; 1498 WORD32 ret; 1499 1500 ps_cur_slice = ps_dec->ps_cur_slice; 1501 if(ps_cur_slice->u1_field_pic_flag) 1502 { 1503 if(ps_dec->u2_prev_ref_frame_num == u2_frame_num) 1504 return 0; 1505 } 1506 1507 u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1; 1508 u4_max_frm_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1509 1510 // check 1511 if(u4_next_frm_num >= u4_max_frm_num) 1512 { 1513 u4_next_frm_num -= u4_max_frm_num; 1514 } 1515 1516 if(u4_next_frm_num == u2_frame_num) 1517 { 1518 return (0); 1519 } 1520 1521 // check 1522 if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL) 1523 && (u4_next_frm_num >= u2_frame_num)) 1524 { 1525 return (0); 1526 } 1527 u4_start_frm_num = u4_next_frm_num; 1528 1529 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1530 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1531 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1532 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1533 s_tmp_poc.i4_delta_pic_order_cnt[0] = 0; 1534 s_tmp_poc.i4_delta_pic_order_cnt[1] = 0; 1535 1536 ps_cur_slice = ps_dec->ps_cur_slice; 1537 ps_pic_params = ps_dec->ps_cur_pps; 1538 1539 i4_frame_gaps = 0; 1540 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1541 1542 /* Find a empty slot to store gap seqn info */ 1543 i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num; 1544 for(i1_gap_idx = 0; i1_gap_idx < MAX_FRAMES; i1_gap_idx++) 1545 { 1546 if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx]) 1547 break; 1548 } 1549 if(MAX_FRAMES == i1_gap_idx) 1550 { 1551 UWORD32 i4_error_code; 1552 i4_error_code = ERROR_DBP_MANAGER_T; 1553 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1554 return i4_error_code; 1555 } 1556 1557 i4_poc = 0; 1558 i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num; 1559 ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1; 1560 pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq; 1561 pi1_gaps_per_seq[i1_gap_idx] = 0; 1562 while(u4_next_frm_num != u2_frame_num) 1563 { 1564 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1565 if(ps_pic_params->ps_sps->u1_pic_order_cnt_type) 1566 { 1567 /* allocate a picture buffer and insert it as ST node */ 1568 ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num, 1569 &ps_dec->s_prev_pic_poc, 1570 &s_tmp_poc, ps_cur_slice, 1571 ps_pic_params, 1, 0, 0, 1572 &i4_poc); 1573 if(ret != OK) 1574 return ret; 1575 1576 /* Display seq no calculations */ 1577 if(i4_poc >= ps_dec->i4_max_poc) 1578 ps_dec->i4_max_poc = i4_poc; 1579 /* IDR Picture or POC wrap around */ 1580 if(i4_poc == 0) 1581 { 1582 ps_dec->i4_prev_max_display_seq = 1583 ps_dec->i4_prev_max_display_seq 1584 + ps_dec->i4_max_poc 1585 + ps_dec->u1_max_dec_frame_buffering 1586 + 1; 1587 ps_dec->i4_max_poc = 0; 1588 } 1589 1590 ps_cur_slice->u1_mmco_equalto5 = 0; 1591 ps_cur_slice->u2_frame_num = u4_next_frm_num; 1592 } 1593 1594 // check 1595 if(ps_dpb_mgr->i1_poc_buf_id_entries 1596 >= ps_dec->u1_max_dec_frame_buffering) 1597 { 1598 ret = ih264d_assign_display_seq(ps_dec); 1599 if(ret != OK) 1600 return ret; 1601 } 1602 1603 ret = ih264d_insert_pic_in_display_list( 1604 ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP, 1605 (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc), 1606 u4_next_frm_num); 1607 if(ret != OK) 1608 return ret; 1609 1610 pi1_gaps_per_seq[i1_gap_idx]++; 1611 ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr, 1612 ps_dec->ps_cur_sps->u1_num_ref_frames); 1613 if(ret != OK) 1614 return ret; 1615 1616 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1617 1618 u4_next_frm_num++; 1619 if(u4_next_frm_num >= u4_max_frm_num) 1620 { 1621 u4_next_frm_num -= u4_max_frm_num; 1622 } 1623 1624 i4_frame_gaps++; 1625 } 1626 1627 return OK; 1628 } 1629 1630 /*! 1631 ************************************************************************** 1632 * \if Function name : ih264d_create_pic_buffers \endif 1633 * 1634 * \brief 1635 * This function creates Picture Buffers. 1636 * 1637 * \return 1638 * 0 on Success and -1 on error 1639 ************************************************************************** 1640 */ 1641 WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf, 1642 dec_struct_t *ps_dec) 1643 { 1644 struct pic_buffer_t *ps_pic_buf; 1645 UWORD8 i; 1646 UWORD32 u4_luma_size, u4_chroma_size; 1647 UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag; 1648 WORD32 j; 1649 UWORD8 *pu1_buf; 1650 1651 ps_pic_buf = ps_dec->ps_pic_buf_base; 1652 ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr); 1653 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr); 1654 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y; 1655 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv; 1656 1657 { 1658 if(ps_dec->u4_share_disp_buf == 1) 1659 { 1660 /* In case of buffers getting shared between application and library 1661 there is no need of reference memtabs. Instead of setting the i4_size 1662 to zero, it is reduced to a small i4_size to ensure that changes 1663 in the code are minimal */ 1664 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1665 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 1666 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 1667 { 1668 u4_luma_size = 64; 1669 } 1670 1671 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1672 { 1673 u4_chroma_size = 64; 1674 } 1675 1676 } 1677 } 1678 1679 pu1_buf = ps_dec->pu1_pic_buf_base; 1680 1681 /* Allocate memory for refernce buffers */ 1682 for(i = 0; i < u1_num_of_buf; i++) 1683 { 1684 UWORD32 u4_offset; 1685 WORD32 buf_ret; 1686 UWORD8 *pu1_luma, *pu1_chroma; 1687 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1688 1689 pu1_luma = pu1_buf; 1690 pu1_buf += ALIGN64(u4_luma_size); 1691 pu1_chroma = pu1_buf; 1692 pu1_buf += ALIGN64(u4_chroma_size); 1693 1694 /* Offset to the start of the pic from the top left corner of the frame 1695 buffer */ 1696 1697 if((0 == ps_dec->u4_share_disp_buf) 1698 || (NULL == ps_dec->disp_bufs[i].buf[0])) 1699 { 1700 UWORD32 pad_len_h, pad_len_v; 1701 1702 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1703 ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset; 1704 1705 pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1)); 1706 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1707 1708 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1709 1710 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1711 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1712 1713 } 1714 else 1715 { 1716 UWORD32 pad_len_h, pad_len_v; 1717 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1718 ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0] 1719 + u4_offset; 1720 1721 ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset; 1722 1723 if(ps_dec->u1_chroma_format == IV_YUV_420P) 1724 { 1725 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 1726 (PAD_LEN_Y_H >> 1)); 1727 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1728 1729 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1730 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1731 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1732 1733 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 1734 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 1735 1736 } 1737 else 1738 { 1739 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 1740 (PAD_LEN_Y_H >> 1)); 1741 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1742 1743 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1744 ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 1745 + u4_offset; 1746 ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 1747 + u4_offset; 1748 1749 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 1750 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 1751 } 1752 } 1753 1754 ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y; 1755 ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv; 1756 ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y; 1757 ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv; 1758 1759 ps_pic_buf->u1_pic_buf_id = i; 1760 1761 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1762 ps_pic_buf, i); 1763 if(0 != buf_ret) 1764 { 1765 ps_dec->i4_error_code = ERROR_BUF_MGR; 1766 return ERROR_BUF_MGR; 1767 } 1768 1769 ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf; 1770 ps_pic_buf++; 1771 } 1772 1773 if(1 == ps_dec->u4_share_disp_buf) 1774 { 1775 for(i = 0; i < u1_num_of_buf; i++) 1776 ps_dec->u4_disp_buf_mapping[i] = 1; 1777 } 1778 return OK; 1779 } 1780 1781 /*! 1782 ************************************************************************** 1783 * \if Function name : ih264d_allocate_dynamic_bufs \endif 1784 * 1785 * \brief 1786 * This function allocates memory required by Decoder. 1787 * 1788 * \param ps_dec: Pointer to dec_struct_t. 1789 * 1790 * \return 1791 * Returns i4_status as returned by MemManager. 1792 * 1793 ************************************************************************** 1794 */ 1795 WORD16 ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec) 1796 { 1797 struct MemReq s_MemReq; 1798 struct MemBlock *p_MemBlock; 1799 1800 pred_info_t *ps_pred_frame; 1801 dec_mb_info_t *ps_frm_mb_info; 1802 dec_slice_struct_t *ps_dec_slice_buf; 1803 UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map; 1804 UWORD16 *pu2_slice_num_map; 1805 1806 WORD16 *pi16_res_coeff; 1807 WORD16 i16_status = 0; 1808 UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag); 1809 UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y; 1810 UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv; 1811 WORD8 c_i = 0; 1812 dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps; 1813 UWORD32 u4_total_mbs = ps_sps->u2_total_num_of_mbs << uc_frmOrFld; 1814 UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs; 1815 UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs; 1816 UWORD32 u4_blk_wd; 1817 UWORD32 ui_size = 0; 1818 UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0; 1819 UWORD8 *pu1_buf; 1820 WORD32 num_entries; 1821 WORD32 size; 1822 void *pv_buf; 1823 UWORD32 u4_num_bufs; 1824 UWORD32 u4_luma_size, u4_chroma_size; 1825 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1826 1827 size = u4_total_mbs; 1828 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1829 RETURN_IF((NULL == pv_buf), IV_FAIL); 1830 ps_dec->pu1_dec_mb_map = pv_buf; 1831 1832 size = u4_total_mbs; 1833 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1834 RETURN_IF((NULL == pv_buf), IV_FAIL); 1835 ps_dec->pu1_recon_mb_map = pv_buf; 1836 1837 size = u4_total_mbs * sizeof(UWORD16); 1838 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1839 RETURN_IF((NULL == pv_buf), IV_FAIL); 1840 ps_dec->pu2_slice_num_map = pv_buf; 1841 1842 /************************************************************/ 1843 /* Post allocation Initialisations */ 1844 /************************************************************/ 1845 ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1846 ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1847 ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1848 1849 ps_dec->ps_pred_start = ps_dec->ps_pred; 1850 1851 size = sizeof(parse_pmbarams_t) * (ps_dec->u1_recon_mb_grp); 1852 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1853 RETURN_IF((NULL == pv_buf), IV_FAIL); 1854 memset(pv_buf, 0, size); 1855 ps_dec->ps_parse_mb_data = pv_buf; 1856 1857 size = sizeof(parse_part_params_t) 1858 * ((ps_dec->u1_recon_mb_grp) << 4); 1859 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1860 RETURN_IF((NULL == pv_buf), IV_FAIL); 1861 ps_dec->ps_parse_part_params = pv_buf; 1862 1863 size = ((u4_wd_mbs * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld); 1864 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1865 RETURN_IF((NULL == pv_buf), IV_FAIL); 1866 ps_dec->ps_deblk_top_mb = pv_buf; 1867 1868 size = ((sizeof(ctxt_inc_mb_info_t)) 1869 * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1)); 1870 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1871 RETURN_IF((NULL == pv_buf), IV_FAIL); 1872 ps_dec->p_ctxt_inc_mb_map = pv_buf; 1873 1874 /* 0th entry of CtxtIncMbMap will be always be containing default values 1875 for CABAC context representing MB not available */ 1876 ps_dec->p_ctxt_inc_mb_map += 1; 1877 1878 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 1879 * 16); 1880 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1881 RETURN_IF((NULL == pv_buf), IV_FAIL); 1882 ps_dec->ps_mv_p[0] = pv_buf; 1883 1884 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 1885 * 16); 1886 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1887 RETURN_IF((NULL == pv_buf), IV_FAIL); 1888 ps_dec->ps_mv_p[1] = pv_buf; 1889 1890 { 1891 UWORD8 i; 1892 for(i = 0; i < MV_SCRATCH_BUFS; i++) 1893 { 1894 size = (sizeof(mv_pred_t) 1895 * ps_dec->u1_recon_mb_grp * 4); 1896 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1897 RETURN_IF((NULL == pv_buf), IV_FAIL); 1898 ps_dec->ps_mv_top_p[i] = pv_buf; 1899 } 1900 } 1901 1902 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1903 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1904 RETURN_IF((NULL == pv_buf), IV_FAIL); 1905 ps_dec->pu1_y_intra_pred_line = pv_buf; 1906 memset(ps_dec->pu1_y_intra_pred_line, 0, size); 1907 ps_dec->pu1_y_intra_pred_line += MB_SIZE; 1908 1909 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1910 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1911 RETURN_IF((NULL == pv_buf), IV_FAIL); 1912 ps_dec->pu1_u_intra_pred_line = pv_buf; 1913 memset(ps_dec->pu1_u_intra_pred_line, 0, size); 1914 ps_dec->pu1_u_intra_pred_line += MB_SIZE; 1915 1916 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1917 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1918 RETURN_IF((NULL == pv_buf), IV_FAIL); 1919 ps_dec->pu1_v_intra_pred_line = pv_buf; 1920 memset(ps_dec->pu1_v_intra_pred_line, 0, size); 1921 ps_dec->pu1_v_intra_pred_line += MB_SIZE; 1922 1923 if(ps_dec->u1_separate_parse) 1924 { 1925 /* Needs one extra row of info, to hold top row data */ 1926 size = sizeof(mb_neigbour_params_t) 1927 * 2 * ((u4_wd_mbs + 2) * (u4_ht_mbs + 1)); 1928 } 1929 else 1930 { 1931 size = sizeof(mb_neigbour_params_t) 1932 * 2 * ((u4_wd_mbs + 2) << uc_frmOrFld); 1933 } 1934 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1935 RETURN_IF((NULL == pv_buf), IV_FAIL); 1936 1937 ps_dec->ps_nbr_mb_row = pv_buf; 1938 memset(ps_dec->ps_nbr_mb_row, 0, size); 1939 1940 /* Allocate deblock MB info */ 1941 size = (u4_total_mbs + u4_wd_mbs) * sizeof(deblk_mb_t); 1942 1943 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1944 RETURN_IF((NULL == pv_buf), IV_FAIL); 1945 ps_dec->ps_deblk_pic = pv_buf; 1946 1947 memset(ps_dec->ps_deblk_pic, 0, size); 1948 1949 /* Allocate frame level mb info */ 1950 size = sizeof(dec_mb_info_t) * u4_total_mbs; 1951 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1952 RETURN_IF((NULL == pv_buf), IV_FAIL); 1953 ps_dec->ps_frm_mb_info = pv_buf; 1954 memset(ps_dec->ps_frm_mb_info, 0, size); 1955 1956 /* Allocate memory for slice headers dec_slice_struct_t */ 1957 num_entries = MAX_FRAMES; 1958 if((1 >= ps_dec->ps_cur_sps->u1_num_ref_frames) && 1959 (0 == ps_dec->i4_display_delay)) 1960 { 1961 num_entries = 1; 1962 } 1963 num_entries = ((2 * num_entries) + 1); 1964 num_entries *= 2; 1965 1966 size = num_entries * sizeof(void *); 1967 size += PAD_MAP_IDX_POC * sizeof(void *); 1968 size *= u4_total_mbs; 1969 size += sizeof(dec_slice_struct_t) * u4_total_mbs; 1970 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1971 RETURN_IF((NULL == pv_buf), IV_FAIL); 1972 1973 ps_dec->ps_dec_slice_buf = pv_buf; 1974 memset(ps_dec->ps_dec_slice_buf, 0, size); 1975 pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf; 1976 pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs; 1977 ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf; 1978 1979 /* Allocate memory for packed pred info */ 1980 num_entries = u4_total_mbs; 1981 num_entries *= 16 * 2; 1982 1983 size = sizeof(pred_info_pkd_t) * num_entries; 1984 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1985 RETURN_IF((NULL == pv_buf), IV_FAIL); 1986 ps_dec->ps_pred_pkd = pv_buf; 1987 1988 /* Allocate memory for coeff data */ 1989 size = MB_LUM_SIZE * sizeof(WORD16); 1990 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent 1991 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent 1992 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */ 1993 size += u4_total_mbs * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t)) 1994 + 9 * sizeof(tu_sblk4x4_coeff_data_t)); 1995 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data 1996 size += u4_total_mbs * 32; 1997 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1998 RETURN_IF((NULL == pv_buf), IV_FAIL); 1999 2000 ps_dec->pi2_coeff_data = pv_buf; 2001 2002 ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE); 2003 2004 /* Allocate MV bank buffer */ 2005 { 2006 UWORD32 col_flag_buffer_size, mvpred_buffer_size; 2007 2008 col_flag_buffer_size = ((ps_dec->u2_pic_wd * ps_dec->u2_pic_ht) >> 4); 2009 mvpred_buffer_size = sizeof(mv_pred_t) 2010 * ((ps_dec->u2_pic_wd * (ps_dec->u2_pic_ht + PAD_MV_BANK_ROW)) >> 4); 2011 2012 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2013 2014 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs); 2015 u4_num_bufs = MAX(u4_num_bufs, 2); 2016 size = ALIGN64(mvpred_buffer_size) + ALIGN64(col_flag_buffer_size); 2017 size *= u4_num_bufs; 2018 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2019 RETURN_IF((NULL == pv_buf), IV_FAIL); 2020 ps_dec->pu1_mv_bank_buf_base = pv_buf; 2021 } 2022 2023 /* Allocate Pic buffer */ 2024 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y; 2025 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv; 2026 2027 { 2028 if(ps_dec->u4_share_disp_buf == 1) 2029 { 2030 /* In case of buffers getting shared between application and library 2031 there is no need of reference memtabs. Instead of setting the i4_size 2032 to zero, it is reduced to a small i4_size to ensure that changes 2033 in the code are minimal */ 2034 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2035 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 2036 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 2037 { 2038 u4_luma_size = 64; 2039 } 2040 2041 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2042 { 2043 u4_chroma_size = 64; 2044 } 2045 2046 } 2047 } 2048 2049 size = ALIGN64(u4_luma_size) + ALIGN64(u4_chroma_size); 2050 size *= ps_dec->u1_pic_bufs; 2051 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2052 RETURN_IF((NULL == pv_buf), IV_FAIL); 2053 ps_dec->pu1_pic_buf_base = pv_buf; 2054 2055 /* Post allocation Increment Actions */ 2056 2057 /***************************************************************************/ 2058 /*Initialize cabac context pointers for every SE that has fixed contextIdx */ 2059 /***************************************************************************/ 2060 { 2061 bin_ctxt_model_t * const p_cabac_ctxt_table_t = 2062 ps_dec->p_cabac_ctxt_table_t; 2063 bin_ctxt_model_t * * p_coeff_abs_level_minus1_t = 2064 ps_dec->p_coeff_abs_level_minus1_t; 2065 bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t; 2066 2067 ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t 2068 + MB_FIELD_DECODING_FLAG; 2069 ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t 2070 + PREV_INTRA4X4_PRED_MODE_FLAG; 2071 ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t 2072 + REM_INTRA4X4_PRED_MODE; 2073 ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t 2074 + INTRA_CHROMA_PRED_MODE; 2075 ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA; 2076 ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX; 2077 ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X; 2078 ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y; 2079 p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0; 2080 p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4; 2081 p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8; 2082 p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12; 2083 p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16; 2084 ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA; 2085 ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA; 2086 2087 p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2088 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET; 2089 2090 p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2091 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET; 2092 2093 p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t 2094 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET; 2095 2096 p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2097 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET; 2098 2099 p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2100 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET; 2101 2102 p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t 2103 + COEFF_ABS_LEVEL_MINUS1_8X8 2104 + COEFF_ABS_LEVEL_CAT_5_OFFSET; 2105 2106 /********************************************************/ 2107 /* context for the high profile related syntax elements */ 2108 /* This is maintained seperately in s_high_profile */ 2109 /********************************************************/ 2110 { 2111 2112 ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t 2113 + TRANSFORM_SIZE_8X8_FLAG; 2114 2115 ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t 2116 + SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2117 2118 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame = 2119 p_cabac_ctxt_table_t 2120 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2121 2122 ps_dec->s_high_profile.ps_coeff_abs_levelminus1 = 2123 p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8; 2124 2125 ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t 2126 + SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2127 2128 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field = 2129 p_cabac_ctxt_table_t 2130 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2131 } 2132 } 2133 return (i16_status); 2134 } 2135 2136 /*! 2137 ************************************************************************** 2138 * \if Function name : ih264d_free_dynamic_bufs \endif 2139 * 2140 * \brief 2141 * This function frees dynamic memory allocated by Decoder. 2142 * 2143 * \param ps_dec: Pointer to dec_struct_t. 2144 * 2145 * \return 2146 * Returns i4_status as returned by MemManager. 2147 * 2148 ************************************************************************** 2149 */ 2150 WORD16 ih264d_free_dynamic_bufs(dec_struct_t * ps_dec) 2151 { 2152 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic); 2153 2154 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_pic); 2155 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_dec_mb_map); 2156 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_recon_mb_map); 2157 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu2_slice_num_map); 2158 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_slice_buf); 2159 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_frm_mb_info); 2160 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_coeff_data); 2161 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_mb_data); 2162 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_part_params); 2163 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_top_mb); 2164 2165 if(ps_dec->p_ctxt_inc_mb_map) 2166 { 2167 ps_dec->p_ctxt_inc_mb_map -= 1; 2168 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_ctxt_inc_mb_map); 2169 } 2170 2171 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[0]); 2172 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[1]); 2173 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred_pkd); 2174 { 2175 UWORD8 i; 2176 for(i = 0; i < MV_SCRATCH_BUFS; i++) 2177 { 2178 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_top_p[i]); 2179 } 2180 } 2181 2182 if(ps_dec->pu1_y_intra_pred_line) 2183 { 2184 ps_dec->pu1_y_intra_pred_line -= MB_SIZE; 2185 } 2186 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_y_intra_pred_line); 2187 2188 if(ps_dec->pu1_u_intra_pred_line) 2189 { 2190 ps_dec->pu1_u_intra_pred_line -= MB_SIZE; 2191 } 2192 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_u_intra_pred_line); 2193 2194 if(ps_dec->pu1_v_intra_pred_line) 2195 { 2196 ps_dec->pu1_v_intra_pred_line -= MB_SIZE; 2197 } 2198 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_v_intra_pred_line); 2199 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_nbr_mb_row); 2200 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mv_bank_buf_base); 2201 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_pic_buf_base); 2202 return 0; 2203 } 2204 2205 /*! 2206 ************************************************************************** 2207 * \if Function name : ih264d_create_mv_bank \endif 2208 * 2209 * \brief 2210 * This function creates MV bank. 2211 * 2212 * \param memType : Type of memory being handled 2213 * 0: Display Buffer 2214 * 1: Decoder Buffer 2215 * 2: Internal Buffer 2216 * \param u1_num_of_buf: Number of decode or display buffers. 2217 * \param u4_wd : Frame width. 2218 * \param u4_ht : Frame Height. 2219 * \param ps_pic_buf_api : Pointer to Picture Buffer API. 2220 * \param ih264d_dec_mem_manager : Memory manager utility supplied by system. 2221 * 2222 * \return 2223 * 0 on Success and -1 on error 2224 * 2225 ************************************************************************** 2226 */ 2227 WORD32 ih264d_create_mv_bank(void *pv_dec, 2228 UWORD32 ui_width, 2229 UWORD32 ui_height) 2230 { 2231 UWORD8 i; 2232 UWORD32 col_flag_buffer_size, mvpred_buffer_size; 2233 UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base; 2234 col_mv_buf_t *ps_col_mv; 2235 mv_pred_t *ps_mv; 2236 UWORD8 *pu1_col_zero_flag_buf; 2237 dec_struct_t *ps_dec = (dec_struct_t *)pv_dec; 2238 WORD32 buf_ret; 2239 UWORD32 u4_num_bufs; 2240 UWORD8 *pu1_buf; 2241 WORD32 size; 2242 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 2243 2244 col_flag_buffer_size = ((ui_width * ui_height) >> 4); 2245 mvpred_buffer_size = sizeof(mv_pred_t) 2246 * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4); 2247 2248 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr); 2249 2250 ps_col_mv = ps_dec->ps_col_mv_base; 2251 2252 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2253 2254 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs); 2255 u4_num_bufs = MAX(u4_num_bufs, 2); 2256 pu1_buf = ps_dec->pu1_mv_bank_buf_base; 2257 for(i = 0 ; i < u4_num_bufs ; i++) 2258 { 2259 pu1_col_zero_flag_buf = pu1_buf; 2260 pu1_buf += ALIGN64(col_flag_buffer_size); 2261 2262 ps_mv = (mv_pred_t *)pu1_buf; 2263 pu1_buf += ALIGN64(mvpred_buffer_size); 2264 2265 memset(ps_mv, 0, ((ui_width * OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t)); 2266 ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4; 2267 2268 ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf; 2269 ps_col_mv->pv_mv = (void *)ps_mv; 2270 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i); 2271 if(0 != buf_ret) 2272 { 2273 ps_dec->i4_error_code = ERROR_BUF_MGR; 2274 return ERROR_BUF_MGR; 2275 } 2276 ps_col_mv++; 2277 } 2278 return OK; 2279 } 2280 2281 void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4, 2282 WORD16 *pi2_out_coeff_data, 2283 UWORD8 *pu1_inv_scan) 2284 { 2285 UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map; 2286 WORD32 idx; 2287 WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0]; 2288 2289 while(u2_sig_coeff_map) 2290 { 2291 idx = CLZ(u2_sig_coeff_map); 2292 2293 idx = 31 - idx; 2294 RESET_BIT(u2_sig_coeff_map,idx); 2295 2296 idx = pu1_inv_scan[idx]; 2297 pi2_out_coeff_data[idx] = *pi2_coeff_data++; 2298 2299 } 2300 } 2301
