1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 /*****************************************************************************/ 21 /* */ 22 /* File Name : decoder_api_main.c */ 23 /* */ 24 /* Description : Functions which recieve the API call from user */ 25 /* */ 26 /* List of Functions : <List the functions defined in this file> */ 27 /* */ 28 /* Issues / Problems : None */ 29 /* */ 30 /* Revision History : */ 31 /* */ 32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 33 /* 30 05 2007 Rajneesh Creation */ 34 /* */ 35 /*****************************************************************************/ 36 37 /*****************************************************************************/ 38 /* File Includes */ 39 /*****************************************************************************/ 40 41 /* System include files */ 42 #include <stdio.h> 43 #include <stdlib.h> 44 #include <stddef.h> 45 #include <string.h> 46 47 /* User include files */ 48 #include "iv_datatypedef.h" 49 #include "iv.h" 50 #include "ivd.h" 51 #include "ithread.h" 52 53 #include "impeg2_job_queue.h" 54 #include "impeg2_macros.h" 55 #include "impeg2_buf_mgr.h" 56 #include "impeg2_disp_mgr.h" 57 #include "impeg2_defs.h" 58 #include "impeg2_platform_macros.h" 59 #include "impeg2_inter_pred.h" 60 #include "impeg2_idct.h" 61 #include "impeg2_format_conv.h" 62 #include "impeg2_mem_func.h" 63 64 #include "impeg2d.h" 65 #include "impeg2d_api.h" 66 #include "impeg2d_bitstream.h" 67 #include "impeg2d_debug.h" 68 #include "impeg2d_structs.h" 69 #include "impeg2d_mc.h" 70 #include "impeg2d_pic_proc.h" 71 #include "impeg2d_deinterlace.h" 72 73 #define NUM_FRAMES_LIMIT_ENABLED 0 74 75 #ifdef LOGO_EN 76 #include "impeg2_ittiam_logo.h" 77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht); 78 #else 79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) 80 #endif 81 82 #if NUM_FRAMES_LIMIT_ENABLED 83 #define NUM_FRAMES_LIMIT 10000 84 #else 85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF 86 #endif 87 88 #define CODEC_NAME "MPEG2VDEC" 89 #define CODEC_RELEASE_TYPE "eval" 90 #define CODEC_RELEASE_VER "01.00" 91 #define CODEC_VENDOR "ITTIAM" 92 93 #ifdef __ANDROID__ 94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 95 strcpy(version_string,"@(#)Id:"); \ 96 strcat(version_string,codec_name); \ 97 strcat(version_string,"_"); \ 98 strcat(version_string,codec_release_type); \ 99 strcat(version_string," Ver:"); \ 100 strcat(version_string,codec_release_ver); \ 101 strcat(version_string," Released by "); \ 102 strcat(version_string,codec_vendor); 103 #else 104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 105 strcpy(version_string,"@(#)Id:"); \ 106 strcat(version_string,codec_name); \ 107 strcat(version_string,"_"); \ 108 strcat(version_string,codec_release_type); \ 109 strcat(version_string," Ver:"); \ 110 strcat(version_string,codec_release_ver); \ 111 strcat(version_string," Released by "); \ 112 strcat(version_string,codec_vendor); \ 113 strcat(version_string," Build: "); \ 114 strcat(version_string,__DATE__); \ 115 strcat(version_string," @ "); \ 116 strcat(version_string,__TIME__); 117 #endif 118 119 120 #define MIN_OUT_BUFS_420 3 121 #define MIN_OUT_BUFS_422ILE 1 122 #define MIN_OUT_BUFS_RGB565 1 123 #define MIN_OUT_BUFS_420SP 2 124 125 126 void impeg2d_init_arch(void *pv_codec); 127 void impeg2d_init_function_ptr(void *pv_codec); 128 129 /*****************************************************************************/ 130 /* */ 131 /* Function Name : impeg2d_api_rel_display_frame */ 132 /* */ 133 /* Description : Release displ buffers that will be shared between decoder */ 134 /* and application */ 135 /* Inputs : Error message */ 136 /* Globals : None */ 137 /* Processing : Just prints error message to console */ 138 /* Outputs : Error mesage to the console */ 139 /* Returns : None */ 140 /* */ 141 /* Issues : <List any issues or problems with this function> */ 142 /* */ 143 /* Revision History: */ 144 /* */ 145 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 146 /* 27 05 2006 Sankar Creation */ 147 /* */ 148 /*****************************************************************************/ 149 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl, 150 void *pv_api_ip, 151 void *pv_api_op) 152 { 153 154 ivd_rel_display_frame_ip_t *dec_rel_disp_ip; 155 ivd_rel_display_frame_op_t *dec_rel_disp_op; 156 157 dec_state_t *ps_dec_state; 158 dec_state_multi_core_t *ps_dec_state_multi_core; 159 160 161 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 162 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op; 163 164 dec_rel_disp_op->u4_error_code = 0; 165 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 166 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 167 168 169 /* If not in shared disp buf mode, return */ 170 if(0 == ps_dec_state->u4_share_disp_buf) 171 return IV_SUCCESS; 172 173 if(NULL == ps_dec_state->pv_pic_buf_mg) 174 return IV_SUCCESS; 175 176 177 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP); 178 179 return IV_SUCCESS; 180 } 181 182 /*****************************************************************************/ 183 /* */ 184 /* Function Name : impeg2d_api_set_display_frame */ 185 /* */ 186 /* Description : Sets display buffers that will be shared between decoder */ 187 /* and application */ 188 /* Inputs : Error message */ 189 /* Globals : None */ 190 /* Processing : Just prints error message to console */ 191 /* Outputs : Error mesage to the console */ 192 /* Returns : None */ 193 /* */ 194 /* Issues : <List any issues or problems with this function> */ 195 /* */ 196 /* Revision History: */ 197 /* */ 198 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 199 /* 27 05 2006 Sankar Creation */ 200 /* */ 201 /*****************************************************************************/ 202 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl, 203 void *pv_api_ip, 204 void *pv_api_op) 205 { 206 207 ivd_set_display_frame_ip_t *dec_disp_ip; 208 ivd_set_display_frame_op_t *dec_disp_op; 209 210 UWORD32 i; 211 dec_state_t *ps_dec_state; 212 dec_state_multi_core_t *ps_dec_state_multi_core; 213 UWORD32 u4_num_disp_bufs; 214 215 216 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 217 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 218 dec_disp_op->u4_error_code = 0; 219 220 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs; 221 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT) 222 u4_num_disp_bufs = BUF_MGR_MAX_CNT; 223 224 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 225 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 226 227 if(ps_dec_state->u4_share_disp_buf) 228 { 229 pic_buf_t *ps_pic_buf; 230 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base; 231 for(i = 0; i < u4_num_disp_bufs; i++) 232 { 233 234 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 235 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat) 236 { 237 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 238 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 239 } 240 else 241 { 242 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i]; 243 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] + 244 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2); 245 } 246 247 ps_pic_buf->i4_buf_id = i; 248 249 ps_pic_buf->u1_used_as_ref = 0; 250 251 ps_pic_buf->u4_ts = 0; 252 253 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i); 254 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP); 255 ps_pic_buf++; 256 257 } 258 } 259 memcpy(&(ps_dec_state->as_disp_buffers[0]), 260 &(dec_disp_ip->s_disp_buffer), 261 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t)); 262 263 return IV_SUCCESS; 264 265 } 266 267 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl, 268 void *pv_api_ip, 269 void *pv_api_op) 270 { 271 impeg2d_ctl_set_num_cores_ip_t *ps_ip; 272 impeg2d_ctl_set_num_cores_op_t *ps_op; 273 dec_state_t *ps_dec_state; 274 dec_state_multi_core_t *ps_dec_state_multi_core; 275 276 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip; 277 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op; 278 279 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 280 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 281 282 if(ps_ip->u4_num_cores > 0) 283 { 284 285 286 WORD32 i; 287 for(i = 0; i < MAX_THREADS; i++) 288 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores; 289 } 290 else 291 { 292 ps_dec_state->i4_num_cores = 1; 293 } 294 ps_op->u4_error_code = IV_SUCCESS; 295 296 return IV_SUCCESS; 297 } 298 299 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl, 300 void *pv_api_ip, 301 void *pv_api_op) 302 { 303 impeg2d_ctl_get_seq_info_ip_t *ps_ip; 304 impeg2d_ctl_get_seq_info_op_t *ps_op; 305 dec_state_t *ps_codec; 306 dec_state_multi_core_t *ps_dec_state_multi_core; 307 308 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip; 309 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op; 310 311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 312 ps_codec = ps_dec_state_multi_core->ps_dec_state[0]; 313 UNUSED(ps_ip); 314 if(ps_codec->u2_header_done == 1) 315 { 316 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info; 317 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code; 318 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n; 319 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d; 320 if(ps_codec->u1_seq_disp_extn_present == 1) 321 { 322 ps_op->u1_video_format = ps_codec->u1_video_format; 323 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries; 324 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics; 325 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients; 326 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size; 327 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size; 328 } 329 else 330 { 331 ps_op->u1_video_format = 5; 332 ps_op->u1_colour_primaries = 2; 333 ps_op->u1_transfer_characteristics = 2; 334 ps_op->u1_matrix_coefficients = 2; 335 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size; 336 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size; 337 } 338 ps_op->u4_error_code = IV_SUCCESS; 339 return IV_SUCCESS; 340 } 341 else 342 { 343 ps_op->u4_error_code = IV_FAIL; 344 return IV_FAIL; 345 } 346 } 347 348 /** 349 ******************************************************************************* 350 * 351 * @brief 352 * Sets Processor type 353 * 354 * @par Description: 355 * Sets Processor type 356 * 357 * @param[in] ps_codec_obj 358 * Pointer to codec object at API level 359 * 360 * @param[in] pv_api_ip 361 * Pointer to input argument structure 362 * 363 * @param[out] pv_api_op 364 * Pointer to output argument structure 365 * 366 * @returns Status 367 * 368 * @remarks 369 * 370 * 371 ******************************************************************************* 372 */ 373 374 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj, 375 void *pv_api_ip, 376 void *pv_api_op) 377 { 378 impeg2d_ctl_set_processor_ip_t *ps_ip; 379 impeg2d_ctl_set_processor_op_t *ps_op; 380 dec_state_t *ps_codec; 381 dec_state_multi_core_t *ps_dec_state_multi_core; 382 383 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle); 384 ps_codec = ps_dec_state_multi_core->ps_dec_state[0]; 385 386 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip; 387 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op; 388 389 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 390 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 391 392 impeg2d_init_function_ptr(ps_codec); 393 394 395 ps_op->u4_error_code = 0; 396 return IV_SUCCESS; 397 } 398 /*****************************************************************************/ 399 /* */ 400 /* Function Name : impeg2d_fill_mem_rec */ 401 /* */ 402 /* Description : */ 403 /* Inputs : */ 404 /* Globals : */ 405 /* Processing : */ 406 /* Outputs : */ 407 /* Returns : */ 408 /* */ 409 /* Issues : */ 410 /* */ 411 /* Revision History: */ 412 /* */ 413 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 414 /* 17 09 2007 Rajendra C Y Draft */ 415 /* */ 416 /*****************************************************************************/ 417 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip, 418 impeg2d_fill_mem_rec_op_t *ps_op) 419 { 420 UWORD32 u4_i; 421 422 UWORD8 u1_no_rec = 0; 423 UWORD32 max_frm_width,max_frm_height,max_frm_size; 424 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 425 WORD32 i4_num_threads; 426 WORD32 i4_share_disp_buf, i4_chroma_format; 427 WORD32 i4_chroma_size; 428 UWORD32 u4_deinterlace; 429 UNUSED(u4_deinterlace); 430 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd); 431 /* In error clips with field prediction, the mv may incorrectly refer to 432 * the last MB row, causing an out of bounds read access. Allocating 8 extra 433 * rows to handle this. Adding another extra row to handle half_y prediction. 434 */ 435 max_frm_height = ALIGN32(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht) + 9; 436 437 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */ 438 439 i4_chroma_size = max_frm_width * max_frm_height / 4; 440 441 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf)) 442 { 443 #ifndef LOGO_EN 444 i4_share_disp_buf = ps_ip->u4_share_disp_buf; 445 #else 446 i4_share_disp_buf = 0; 447 #endif 448 } 449 else 450 { 451 i4_share_disp_buf = 0; 452 } 453 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format)) 454 { 455 i4_chroma_format = ps_ip->e_output_format; 456 } 457 else 458 { 459 i4_chroma_format = -1; 460 } 461 462 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace)) 463 { 464 u4_deinterlace = ps_ip->u4_deinterlace; 465 } 466 else 467 { 468 u4_deinterlace = 0; 469 } 470 471 472 if( (i4_chroma_format != IV_YUV_420P) && 473 (i4_chroma_format != IV_YUV_420SP_UV) && 474 (i4_chroma_format != IV_YUV_420SP_VU)) 475 { 476 i4_share_disp_buf = 0; 477 } 478 479 /* Disable deinterlacer in shared mode */ 480 if(i4_share_disp_buf) 481 { 482 u4_deinterlace = 0; 483 } 484 485 /*************************************************************************/ 486 /* Fill the memory requirement XDM Handle */ 487 /*************************************************************************/ 488 /* ! */ 489 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 490 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 491 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t); 492 493 ps_mem_rec++; 494 u1_no_rec++; 495 496 { 497 /*************************************************************************/ 498 /* Fill the memory requirement for threads context */ 499 /*************************************************************************/ 500 /* ! */ 501 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 502 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 503 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t); 504 505 ps_mem_rec++; 506 u1_no_rec++; 507 } 508 509 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 510 { 511 /*************************************************************************/ 512 /* Fill the memory requirement for MPEG2 Decoder Context */ 513 /*************************************************************************/ 514 /* ! */ 515 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 516 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 517 ps_mem_rec->u4_mem_size = sizeof(dec_state_t); 518 519 ps_mem_rec++; 520 u1_no_rec++; 521 522 /* To store thread handle */ 523 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 524 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 525 ps_mem_rec->u4_mem_size = ithread_get_handle_size(); 526 527 ps_mem_rec++; 528 u1_no_rec++; 529 530 /*************************************************************************/ 531 /* Fill the memory requirement for Motion Compensation Buffers */ 532 /*************************************************************************/ 533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM; 535 536 /* for mc_fw_buf.pu1_y */ 537 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE; 538 539 /* for mc_fw_buf.pu1_u */ 540 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 541 542 /* for mc_fw_buf.pu1_v */ 543 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 544 545 /* for mc_bk_buf.pu1_y */ 546 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE; 547 548 /* for mc_bk_buf.pu1_u */ 549 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 550 551 /* for mc_bk_buf.pu1_v */ 552 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 553 554 /* for mc_buf.pu1_y */ 555 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE; 556 557 /* for mc_buf.pu1_u */ 558 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 559 560 /* for mc_buf.pu1_v */ 561 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 562 563 ps_mem_rec++; 564 u1_no_rec++; 565 566 567 /*************************************************************************/ 568 /* Fill the memory requirement Stack Context */ 569 /*************************************************************************/ 570 /* ! */ 571 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 572 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 573 ps_mem_rec->u4_mem_size = 392; 574 575 ps_mem_rec++; 576 u1_no_rec++; 577 } 578 579 580 581 { 582 /*************************************************************************/ 583 /* Fill the memory requirement for Picture Buffer Manager */ 584 /*************************************************************************/ 585 /* ! */ 586 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 587 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 588 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT; 589 590 ps_mem_rec++; 591 u1_no_rec++; 592 } 593 /*************************************************************************/ 594 /* Internal Frame Buffers */ 595 /*************************************************************************/ 596 /* ! */ 597 598 { 599 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++) 600 { 601 /* ! */ 602 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 603 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 604 if(0 == i4_share_disp_buf) 605 ps_mem_rec->u4_mem_size = max_frm_size; 606 else if(IV_YUV_420P != i4_chroma_format) 607 { 608 /* If color format is not 420P and it is shared, then allocate for chroma */ 609 ps_mem_rec->u4_mem_size = i4_chroma_size * 2; 610 } 611 else 612 ps_mem_rec->u4_mem_size = 64; 613 ps_mem_rec++; 614 u1_no_rec++; 615 } 616 } 617 618 619 620 { 621 WORD32 i4_job_queue_size; 622 WORD32 i4_num_jobs; 623 624 /* One job per row of MBs */ 625 i4_num_jobs = max_frm_height >> 4; 626 627 /* One format convert/frame copy job per row of MBs for non-shared mode*/ 628 i4_num_jobs += max_frm_height >> 4; 629 630 631 i4_job_queue_size = impeg2_jobq_ctxt_size(); 632 i4_job_queue_size += i4_num_jobs * sizeof(job_t); 633 ps_mem_rec->u4_mem_size = i4_job_queue_size; 634 ps_mem_rec->u4_mem_alignment = 128; 635 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 636 637 ps_mem_rec++; 638 u1_no_rec++; 639 640 } 641 642 ps_mem_rec->u4_mem_alignment = 128; 643 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 644 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size(); 645 ps_mem_rec++; 646 u1_no_rec++; 647 648 ps_mem_rec->u4_mem_alignment = 128; 649 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 650 651 if(IV_YUV_420P != i4_chroma_format) 652 ps_mem_rec->u4_mem_size = max_frm_size; 653 else 654 ps_mem_rec->u4_mem_size = 64; 655 656 ps_mem_rec++; 657 u1_no_rec++; 658 659 ps_mem_rec->u4_mem_alignment = 128; 660 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 661 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS); 662 ps_mem_rec++; 663 u1_no_rec++; 664 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec; 665 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0; 666 } 667 668 669 /*****************************************************************************/ 670 /* */ 671 /* Function Name : impeg2d_api_get_version */ 672 /* */ 673 /* Description : */ 674 /* */ 675 /* Inputs : */ 676 /* Globals : <Does it use any global variables?> */ 677 /* Outputs : */ 678 /* Returns : void */ 679 /* */ 680 /* Issues : none */ 681 /* */ 682 /* Revision History: */ 683 /* */ 684 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 685 /* 22 10 2008 100356 Draft */ 686 /* */ 687 /*****************************************************************************/ 688 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl, 689 void *pv_api_ip, 690 void *pv_api_op) 691 { 692 char au1_version_string[512]; 693 694 impeg2d_ctl_getversioninfo_ip_t *ps_ip; 695 impeg2d_ctl_getversioninfo_op_t *ps_op; 696 697 UNUSED(ps_dechdl); 698 699 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip; 700 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op; 701 702 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS; 703 704 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 705 CODEC_VENDOR); 706 707 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0) 708 { 709 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL; 710 return (IV_FAIL); 711 } 712 713 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size 714 >= (strlen(au1_version_string) + 1)) 715 { 716 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer, 717 au1_version_string, (strlen(au1_version_string) + 1)); 718 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS; 719 } 720 else 721 { 722 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL; 723 } 724 725 return (IV_SUCCESS); 726 } 727 728 /*****************************************************************************/ 729 /* */ 730 /* Function Name : impeg2d_api_get_buf_info */ 731 /* */ 732 /* Description : */ 733 /* */ 734 /* Inputs : */ 735 /* Globals : <Does it use any global variables?> */ 736 /* Outputs : */ 737 /* Returns : void */ 738 /* */ 739 /* Issues : none */ 740 /* */ 741 /* Revision History: */ 742 /* */ 743 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 744 /* 22 10 2008 100356 Draft */ 745 /* */ 746 /*****************************************************************************/ 747 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl, 748 void *pv_api_ip, 749 void *pv_api_op) 750 { 751 dec_state_t *ps_dec_state; 752 dec_state_multi_core_t *ps_dec_state_multi_core; 753 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip = 754 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip; 755 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op = 756 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op; 757 UWORD32 u4_i, u4_stride, u4_height; 758 UNUSED(ps_ctl_bufinfo_ip); 759 760 ps_dec_state_multi_core = 761 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle); 762 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 763 764 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1; 765 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1; 766 767 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P) 768 { 769 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 770 MIN_OUT_BUFS_420; 771 } 772 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) 773 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU)) 774 { 775 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 776 MIN_OUT_BUFS_420SP; 777 } 778 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 779 { 780 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 781 MIN_OUT_BUFS_422ILE; 782 } 783 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565) 784 { 785 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 786 MIN_OUT_BUFS_RGB565; 787 } 788 else 789 { 790 //Invalid chroma format; Error code may be updated, verify in testing if needed 791 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 792 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 793 return IV_FAIL; 794 } 795 796 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++) 797 { 798 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] = 799 0; 800 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] = 801 0; 802 } 803 804 for(u4_i = 0; 805 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs; 806 u4_i++) 807 { 808 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] = 809 MAX_BITSTREAM_BUFFER_SIZE; 810 } 811 812 if (0 == ps_dec_state->u4_frm_buf_stride) 813 { 814 if (1 == ps_dec_state->u2_header_done) 815 { 816 u4_stride = ps_dec_state->u2_horizontal_size; 817 } 818 else 819 { 820 u4_stride = ps_dec_state->u2_create_max_width; 821 } 822 } 823 else 824 { 825 u4_stride = ps_dec_state->u4_frm_buf_stride; 826 } 827 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4; 828 829 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P) 830 { 831 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] = 832 (u4_stride * u4_height); 833 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] = 834 (u4_stride * u4_height) >> 2; 835 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] = 836 (u4_stride * u4_height) >> 2; 837 } 838 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) 839 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU)) 840 { 841 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] = 842 (u4_stride * u4_height); 843 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] = 844 (u4_stride * u4_height) >> 1; 845 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] = 0; 846 } 847 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 848 { 849 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] = 850 (u4_stride * u4_height) * 2; 851 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] = 852 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] = 853 0; 854 } 855 856 /* Adding initialization for 2 uninitialized values */ 857 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1; 858 if(ps_dec_state->u4_share_disp_buf) 859 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 860 NUM_INT_FRAME_BUFFERS; 861 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE; 862 863 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS; 864 865 return (IV_SUCCESS); 866 } 867 868 /*****************************************************************************/ 869 /* */ 870 /* Function Name : impeg2d_api_set_flush_mode */ 871 /* */ 872 /* Description : */ 873 /* */ 874 /* Inputs : */ 875 /* Globals : <Does it use any global variables?> */ 876 /* Outputs : */ 877 /* Returns : void */ 878 /* */ 879 /* Issues : none */ 880 /* */ 881 /* Revision History: */ 882 /* */ 883 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 884 /* 08 06 2009 100356 RAVI */ 885 /* */ 886 /*****************************************************************************/ 887 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl, 888 void *pv_api_ip, 889 void *pv_api_op) 890 { 891 dec_state_t *ps_dec_state; 892 dec_state_multi_core_t *ps_dec_state_multi_core; 893 impeg2d_ctl_flush_op_t *ps_ctl_dec_op = 894 (impeg2d_ctl_flush_op_t*)pv_api_op; 895 896 UNUSED(pv_api_ip); 897 898 ps_dec_state_multi_core = 899 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle); 900 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 901 902 ps_dec_state->u1_flushfrm = 1; 903 904 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size = 905 sizeof(impeg2d_ctl_flush_op_t); 906 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS; 907 908 return (IV_SUCCESS); 909 } 910 911 /*****************************************************************************/ 912 /* */ 913 /* Function Name : impeg2d_api_set_default */ 914 /* */ 915 /* Description : */ 916 /* */ 917 /* Inputs : */ 918 /* Globals : <Does it use any global variables?> */ 919 /* Outputs : */ 920 /* Returns : void */ 921 /* */ 922 /* Issues : none */ 923 /* */ 924 /* Revision History: */ 925 /* */ 926 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 927 /* 08 06 2009 100356 RAVI */ 928 /* */ 929 /*****************************************************************************/ 930 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl, 931 void *pv_api_ip, 932 void *pv_api_op) 933 { 934 dec_state_t *ps_dec_state; 935 dec_state_multi_core_t *ps_dec_state_multi_core; 936 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = 937 (impeg2d_ctl_set_config_op_t *)pv_api_op; 938 939 UNUSED(pv_api_ip); 940 941 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS; 942 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size = 943 sizeof(impeg2d_ctl_set_config_op_t); 944 945 ps_dec_state_multi_core = 946 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle); 947 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 948 949 ps_dec_state->u1_flushfrm = 0; 950 ps_dec_state->u2_decode_header = 1; 951 952 if (1 == ps_dec_state->u2_header_done) 953 { 954 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width; 955 } 956 957 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS; 958 959 return (IV_SUCCESS); 960 961 } 962 963 /*****************************************************************************/ 964 /* */ 965 /* Function Name : impeg2d_api_reset */ 966 /* */ 967 /* Description : */ 968 /* */ 969 /* Inputs : */ 970 /* Globals : <Does it use any global variables?> */ 971 /* Outputs : */ 972 /* Returns : void */ 973 /* */ 974 /* Issues : none */ 975 /* */ 976 /* Revision History: */ 977 /* */ 978 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 979 /* 08 06 2009 100356 RAVI */ 980 /* */ 981 /*****************************************************************************/ 982 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl, 983 void *pv_api_ip, 984 void *pv_api_op) 985 { 986 dec_state_t *ps_dec_state; 987 dec_state_multi_core_t *ps_dec_state_multi_core; 988 UNUSED(pv_api_ip); 989 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op; 990 991 WORD32 i4_num_threads; 992 993 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 994 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 995 996 if(ps_dec_state_multi_core != NULL) 997 { 998 if(ps_dec_state->aps_ref_pics[1] != NULL) 999 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF); 1000 if(ps_dec_state->aps_ref_pics[0] != NULL) 1001 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF); 1002 while(1) 1003 { 1004 pic_buf_t *ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id); 1005 if(NULL == ps_disp_pic) 1006 break; 1007 if(0 == ps_dec_state->u4_share_disp_buf) 1008 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP); 1009 1010 } 1011 1012 if((ps_dec_state->u4_deinterlace) && (NULL != ps_dec_state->ps_deint_pic)) 1013 { 1014 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, 1015 ps_dec_state->ps_deint_pic->i4_buf_id, 1016 MPEG2_BUF_MGR_DEINT); 1017 } 1018 1019 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 1020 { 1021 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads]; 1022 1023 1024 /* --------------------------------------------------------------------- */ 1025 /* Initializations */ 1026 1027 ps_dec_state->u2_header_done = 0; /* Header decoding not done */ 1028 ps_dec_state->u4_frm_buf_stride = 0; 1029 ps_dec_state->i4_pic_count = 0; 1030 ps_dec_state->u2_is_mpeg2 = 0; 1031 ps_dec_state->aps_ref_pics[0] = NULL; 1032 ps_dec_state->aps_ref_pics[1] = NULL; 1033 ps_dec_state->ps_deint_pic = NULL; 1034 } 1035 } 1036 else 1037 { 1038 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code = 1039 IMPEG2D_INIT_NOT_DONE; 1040 } 1041 1042 return(IV_SUCCESS); 1043 } 1044 1045 /*****************************************************************************/ 1046 /* */ 1047 /* Function Name : impeg2d_api_set_params */ 1048 /* */ 1049 /* Description : */ 1050 /* */ 1051 /* Inputs : */ 1052 /* Globals : <Does it use any global variables?> */ 1053 /* Outputs : */ 1054 /* Returns : void */ 1055 /* */ 1056 /* Issues : none */ 1057 /* */ 1058 /* Revision History: */ 1059 /* */ 1060 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1061 /* 08 06 2009 100356 RAVI */ 1062 /* */ 1063 /*****************************************************************************/ 1064 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op) 1065 { 1066 dec_state_t *ps_dec_state; 1067 dec_state_multi_core_t *ps_dec_state_multi_core; 1068 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip; 1069 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op; 1070 1071 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 1072 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1073 1074 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME)) 1075 { 1076 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1077 return(IV_FAIL); 1078 } 1079 1080 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT)) 1081 { 1082 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1083 return(IV_FAIL); 1084 } 1085 1086 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE) 1087 { 1088 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1089 return(IV_FAIL); 1090 } 1091 1092 if(ps_dec_state->u2_header_done == 1) 1093 { 1094 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) || 1095 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width))) 1096 { 1097 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1098 return(IV_FAIL); 1099 } 1100 1101 } 1102 1103 1104 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode; 1105 1106 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) 1107 { 1108 if(ps_dec_state->u2_header_done == 1) 1109 { 1110 if (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd > ps_dec_state->u2_frame_width) 1111 { 1112 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd; 1113 } 1114 } 1115 else 1116 { 1117 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd; 1118 } 1119 1120 } 1121 else 1122 { 1123 1124 if(ps_dec_state->u2_header_done == 1) 1125 { 1126 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width; 1127 } 1128 else 1129 { 1130 ps_dec_state->u4_frm_buf_stride = 0; 1131 } 1132 } 1133 1134 1135 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME) 1136 { 1137 ps_dec_state->u1_flushfrm = 0; 1138 } 1139 1140 1141 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS; 1142 return(IV_SUCCESS); 1143 1144 } 1145 1146 /*****************************************************************************/ 1147 /* */ 1148 /* Function Name : impeg2d_api_get_status */ 1149 /* */ 1150 /* Description : */ 1151 /* */ 1152 /* Inputs : */ 1153 /* Globals : <Does it use any global variables?> */ 1154 /* Outputs : */ 1155 /* Returns : void */ 1156 /* */ 1157 /* Issues : none */ 1158 /* */ 1159 /* Revision History: */ 1160 /* */ 1161 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1162 /* 08 06 2009 100356 RAVI */ 1163 /* */ 1164 /*****************************************************************************/ 1165 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl, 1166 void *pv_api_ip, 1167 void *pv_api_op) 1168 { 1169 dec_state_t *ps_dec_state; 1170 dec_state_multi_core_t *ps_dec_state_multi_core; 1171 UWORD32 u4_i,u4_stride,u4_height; 1172 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip; 1173 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op; 1174 UNUSED(ps_ctl_dec_ip); 1175 1176 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 1177 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1178 1179 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t); 1180 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1; 1181 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height; 1182 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width; 1183 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod; 1184 1185 1186 if(ps_dec_state->u2_progressive_sequence == 1) 1187 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ; 1188 else 1189 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED; 1190 1191 1192 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat; 1193 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1; 1194 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1; 1195 1196 1197 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P) 1198 { 1199 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420; 1200 } 1201 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 1202 { 1203 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 1204 } 1205 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565) 1206 { 1207 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 1208 } 1209 else 1210 { 1211 //Invalid chroma format; Error code may be updated, verify in testing if needed 1212 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 1213 return IV_FAIL; 1214 } 1215 1216 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS)); 1217 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS)); 1218 1219 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++) 1220 { 1221 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE; 1222 } 1223 1224 u4_stride = ps_dec_state->u4_frm_buf_stride; 1225 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4; 1226 1227 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P) 1228 { 1229 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height); 1230 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ; 1231 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2; 1232 } 1233 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU)) 1234 { 1235 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height); 1236 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ; 1237 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0; 1238 } 1239 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 1240 { 1241 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2; 1242 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0; 1243 } 1244 1245 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS; 1246 1247 return(IV_SUCCESS); 1248 1249 } 1250 1251 /** 1252 ******************************************************************************* 1253 * 1254 * @brief 1255 * Gets frame dimensions/offsets 1256 * 1257 * @par Description: 1258 * Gets frame buffer chararacteristics such a x & y offsets display and 1259 * buffer dimensions 1260 * 1261 * @param[in] ps_codec_obj 1262 * Pointer to codec object at API level 1263 * 1264 * @param[in] pv_api_ip 1265 * Pointer to input argument structure 1266 * 1267 * @param[out] pv_api_op 1268 * Pointer to output argument structure 1269 * 1270 * @returns Status 1271 * 1272 * @remarks 1273 * 1274 * 1275 ******************************************************************************* 1276 */ 1277 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj, 1278 void *pv_api_ip, 1279 void *pv_api_op) 1280 { 1281 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip; 1282 impeg2d_ctl_get_frame_dimensions_op_t *ps_op; 1283 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 1284 dec_state_t *ps_codec; 1285 dec_state_multi_core_t *ps_dec_state_multi_core; 1286 1287 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle); 1288 ps_codec = ps_dec_state_multi_core->ps_dec_state[0]; 1289 1290 1291 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 1292 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op; 1293 UNUSED(ps_ip); 1294 if(ps_codec->u2_header_done) 1295 { 1296 disp_wd = ps_codec->u2_horizontal_size; 1297 disp_ht = ps_codec->u2_vertical_size; 1298 1299 if(0 == ps_codec->u4_share_disp_buf) 1300 { 1301 buffer_wd = disp_wd; 1302 buffer_ht = disp_ht; 1303 } 1304 else 1305 { 1306 buffer_wd = ps_codec->u2_frame_width; 1307 buffer_ht = ps_codec->u2_frame_height; 1308 } 1309 } 1310 else 1311 { 1312 1313 disp_wd = ps_codec->u2_create_max_width; 1314 disp_ht = ps_codec->u2_create_max_height; 1315 1316 if(0 == ps_codec->u4_share_disp_buf) 1317 { 1318 buffer_wd = disp_wd; 1319 buffer_ht = disp_ht; 1320 } 1321 else 1322 { 1323 buffer_wd = ALIGN16(disp_wd); 1324 buffer_ht = ALIGN16(disp_ht); 1325 1326 } 1327 } 1328 if(ps_codec->u2_frame_width > buffer_wd) 1329 buffer_wd = ps_codec->u2_frame_width; 1330 1331 x_offset = 0; 1332 y_offset = 0; 1333 1334 1335 ps_op->u4_disp_wd[0] = disp_wd; 1336 ps_op->u4_disp_ht[0] = disp_ht; 1337 ps_op->u4_buffer_wd[0] = buffer_wd; 1338 ps_op->u4_buffer_ht[0] = buffer_ht; 1339 ps_op->u4_x_offset[0] = x_offset; 1340 ps_op->u4_y_offset[0] = y_offset; 1341 1342 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 1343 >> 1); 1344 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 1345 >> 1); 1346 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 1347 >> 1); 1348 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 1349 >> 1); 1350 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0] 1351 >> 1); 1352 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0] 1353 >> 1); 1354 1355 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV) 1356 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU)) 1357 { 1358 ps_op->u4_disp_wd[2] = 0; 1359 ps_op->u4_disp_ht[2] = 0; 1360 ps_op->u4_buffer_wd[2] = 0; 1361 ps_op->u4_buffer_ht[2] = 0; 1362 ps_op->u4_x_offset[2] = 0; 1363 ps_op->u4_y_offset[2] = 0; 1364 1365 ps_op->u4_disp_wd[1] <<= 1; 1366 ps_op->u4_buffer_wd[1] <<= 1; 1367 ps_op->u4_x_offset[1] <<= 1; 1368 } 1369 1370 return IV_SUCCESS; 1371 1372 } 1373 1374 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op) 1375 { 1376 WORD32 i4_cmd; 1377 IV_API_CALL_STATUS_T u4_error_code; 1378 UWORD32 *pu4_api_ip; 1379 1380 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op); 1381 if(IV_SUCCESS != u4_error_code) 1382 { 1383 return u4_error_code; 1384 } 1385 1386 1387 pu4_api_ip = (UWORD32 *)pv_api_ip; 1388 i4_cmd = *(pu4_api_ip + 1); 1389 1390 switch(i4_cmd) 1391 { 1392 1393 case IV_CMD_GET_NUM_MEM_REC: 1394 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op); 1395 break; 1396 1397 case IV_CMD_FILL_NUM_MEM_REC: 1398 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op); 1399 break; 1400 1401 case IV_CMD_INIT: 1402 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1403 break; 1404 1405 case IVD_CMD_SET_DISPLAY_FRAME: 1406 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1407 break; 1408 1409 case IVD_CMD_REL_DISPLAY_FRAME: 1410 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1411 break; 1412 1413 case IVD_CMD_VIDEO_DECODE: 1414 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op); 1415 break; 1416 1417 case IV_CMD_RETRIEVE_MEMREC: 1418 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1419 break; 1420 1421 case IVD_CMD_VIDEO_CTL: 1422 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1423 break; 1424 1425 default: 1426 break; 1427 } 1428 1429 return(u4_error_code); 1430 1431 } 1432 1433 /*****************************************************************************/ 1434 /* */ 1435 /* Function Name : impeg2d_api_num_mem_rec */ 1436 /* */ 1437 /* Description : The function get the number mem records library needs */ 1438 /* Inputs : Error message */ 1439 /* Globals : None */ 1440 /* Processing : Just prints error message to console */ 1441 /* Outputs : Error mesage to the console */ 1442 /* Returns : None */ 1443 /* */ 1444 /* Issues : <List any issues or problems with this function> */ 1445 /* */ 1446 /* Revision History: */ 1447 /* */ 1448 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1449 /* 23 09 2010 Hamsalekha Creation */ 1450 /* */ 1451 /*****************************************************************************/ 1452 1453 1454 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op) 1455 { 1456 /* To Query No of Memory Records */ 1457 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip; 1458 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op; 1459 1460 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip; 1461 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op; 1462 1463 UNUSED(ps_query_mem_rec_ip); 1464 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t); 1465 1466 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS; 1467 1468 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS; 1469 1470 1471 return(IV_SUCCESS); 1472 1473 } 1474 1475 1476 /*****************************************************************************/ 1477 /* */ 1478 /* Function Name : impeg2d_api_fill_mem_rec */ 1479 /* */ 1480 /* Description : Thsi functions fills details of each mem record lib needs*/ 1481 /* Inputs : Error message */ 1482 /* Globals : None */ 1483 /* Processing : Just prints error message to console */ 1484 /* Outputs : Error mesage to the console */ 1485 /* Returns : None */ 1486 /* */ 1487 /* Issues : <List any issues or problems with this function> */ 1488 /* */ 1489 /* Revision History: */ 1490 /* */ 1491 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1492 /* 23 09 2010 Hamsalekha Creation */ 1493 /* */ 1494 /*****************************************************************************/ 1495 1496 1497 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op) 1498 { 1499 1500 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip; 1501 impeg2d_fill_mem_rec_op_t *ps_mem_q_op; 1502 1503 1504 ps_mem_q_ip = pv_api_ip; 1505 ps_mem_q_op = pv_api_op; 1506 1507 1508 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip, 1509 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op); 1510 1511 1512 return(IV_SUCCESS); 1513 1514 } 1515 1516 1517 1518 /*****************************************************************************/ 1519 /* */ 1520 /* Function Name : impeg2d_api_init */ 1521 /* */ 1522 /* Description : */ 1523 /* Inputs : */ 1524 /* Globals : */ 1525 /* Processing : */ 1526 /* Outputs : */ 1527 /* Returns : */ 1528 /* */ 1529 /* Issues : */ 1530 /* */ 1531 /* Revision History: */ 1532 /* */ 1533 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1534 /* 17 09 2007 Rajendra C Y Draft */ 1535 /* */ 1536 /*****************************************************************************/ 1537 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl, 1538 void *ps_ip, 1539 void *ps_op) 1540 { 1541 UWORD32 i; 1542 1543 void *pv; 1544 UWORD32 u4_size; 1545 1546 dec_state_t *ps_dec_state; 1547 dec_state_multi_core_t *ps_dec_state_multi_core; 1548 UWORD32 u4_num_mem_rec; 1549 iv_mem_rec_t *ps_mem_rec ; 1550 iv_mem_rec_t *ps_frm_buf; 1551 iv_obj_t *ps_dec_handle; 1552 WORD32 i4_max_wd, i4_max_ht; 1553 1554 impeg2d_init_ip_t *ps_dec_init_ip; 1555 impeg2d_init_op_t *ps_dec_init_op; 1556 WORD32 i4_num_threads; 1557 UWORD32 u4_share_disp_buf, u4_chroma_format; 1558 UWORD32 u4_deinterlace; 1559 1560 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip; 1561 ps_dec_init_op = (impeg2d_init_op_t *)ps_op; 1562 1563 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd); 1564 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht); 1565 1566 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf)) 1567 { 1568 #ifndef LOGO_EN 1569 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf; 1570 #else 1571 u4_share_disp_buf = 0; 1572 #endif 1573 } 1574 else 1575 { 1576 u4_share_disp_buf = 0; 1577 } 1578 1579 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format; 1580 1581 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace)) 1582 { 1583 u4_deinterlace = ps_dec_init_ip->u4_deinterlace; 1584 } 1585 else 1586 { 1587 u4_deinterlace = 0; 1588 } 1589 1590 if( (u4_chroma_format != IV_YUV_420P) && 1591 (u4_chroma_format != IV_YUV_420SP_UV) && 1592 (u4_chroma_format != IV_YUV_420SP_VU)) 1593 { 1594 u4_share_disp_buf = 0; 1595 } 1596 1597 /* Disable deinterlacer in shared mode */ 1598 if(u4_share_disp_buf) 1599 { 1600 u4_deinterlace = 0; 1601 } 1602 1603 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location; 1604 ps_mem_rec ++; 1605 1606 1607 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t); 1608 1609 1610 /* Except memTab[0], all other memTabs are initialized to zero */ 1611 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++) 1612 { 1613 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size); 1614 ps_mem_rec++; 1615 } 1616 1617 /* Reinitializing memTab[0] memory base address */ 1618 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location; 1619 1620 1621 /* memTab[0] is for codec Handle,redundant currently not being used */ 1622 ps_dec_handle = ps_mem_rec->pv_base; 1623 u4_num_mem_rec = 1; 1624 ps_mem_rec++; 1625 1626 1627 1628 1629 1630 /* decoder handle */ 1631 ps_dec_state_multi_core = ps_mem_rec->pv_base; 1632 u4_num_mem_rec++; 1633 ps_mem_rec++; 1634 1635 1636 { 1637 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */ 1638 1639 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core; 1640 ps_dechdl->pv_fxns = (void *)impeg2d_api_function; 1641 } 1642 1643 1644 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 1645 { 1646 /*************************************************************************/ 1647 /* For MPEG2 Decoder Context */ 1648 /*************************************************************************/ 1649 ps_dec_state = ps_mem_rec->pv_base; 1650 1651 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state; 1652 1653 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core; 1654 1655 ps_dec_state->i4_num_cores = 1; 1656 /* @ */ /* Used for storing MemRecords */ 1657 u4_num_mem_rec++; 1658 ps_mem_rec++; 1659 1660 /* Thread handle */ 1661 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base; 1662 u4_num_mem_rec++; 1663 ps_mem_rec++; 1664 1665 /*************************************************************************/ 1666 /* For Motion Compensation Buffers */ 1667 /*************************************************************************/ 1668 pv = ps_mem_rec->pv_base; 1669 1670 /* for mc_fw_buf.pu1_y */ 1671 1672 ps_dec_state->s_mc_fw_buf.pu1_y = pv; 1673 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE); 1674 1675 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE; 1676 /* for mc_fw_buf.pu1_u */ 1677 1678 ps_dec_state->s_mc_fw_buf.pu1_u = pv; 1679 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1680 1681 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1682 1683 /* for mc_fw_buf.pu1_v */ 1684 1685 ps_dec_state->s_mc_fw_buf.pu1_v = pv; 1686 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1687 1688 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1689 1690 /* for mc_bk_buf.pu1_y */ 1691 1692 ps_dec_state->s_mc_bk_buf.pu1_y = pv; 1693 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE); 1694 1695 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE; 1696 1697 /* for mc_bk_buf.pu1_u */ 1698 1699 ps_dec_state->s_mc_bk_buf.pu1_u = pv; 1700 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1701 1702 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1703 1704 /* for mc_bk_buf.pu1_v */ 1705 1706 ps_dec_state->s_mc_bk_buf.pu1_v = pv; 1707 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1708 1709 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1710 1711 /* for mc_buf.pu1_y */ 1712 1713 ps_dec_state->s_mc_buf.pu1_y = pv; 1714 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE); 1715 1716 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE; 1717 1718 /* for mc_buf.pu1_u */ 1719 1720 ps_dec_state->s_mc_buf.pu1_u = pv; 1721 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1722 1723 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1724 1725 /* for mc_buf.pu1_v */ 1726 1727 ps_dec_state->s_mc_buf.pu1_v = pv; 1728 1729 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1730 1731 u4_num_mem_rec++; 1732 ps_mem_rec++; 1733 1734 1735 1736 ps_dec_state->pv_pic_buf_mg = 0; 1737 1738 /*************************************************************************/ 1739 /* For saving stack context to support global error handling */ 1740 /*************************************************************************/ 1741 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base; 1742 u4_num_mem_rec++; 1743 ps_mem_rec++; 1744 1745 } 1746 1747 1748 1749 1750 1751 /*************************************************************************/ 1752 /* For Picture Buffer Manager */ 1753 /*************************************************************************/ 1754 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1755 1756 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base; 1757 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t); 1758 1759 u4_num_mem_rec++; 1760 ps_mem_rec++; 1761 1762 1763 1764 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 1765 { 1766 1767 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads]; 1768 1769 1770 /* --------------------------------------------------------------------- */ 1771 /* Initializations */ 1772 1773 ps_dec_state->u2_header_done = 0; /* Header decoding not done */ 1774 1775 1776 { 1777 UWORD32 u4_max_frm_width,u4_max_frm_height; 1778 1779 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd); 1780 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht); 1781 1782 ps_dec_state->u2_create_max_width = u4_max_frm_width; 1783 ps_dec_state->u2_create_max_height = u4_max_frm_height; 1784 1785 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format; 1786 ps_dec_state->u4_frm_buf_stride = 0 ; 1787 ps_dec_state->u2_frame_width = u4_max_frm_width; 1788 ps_dec_state->u2_picture_width = u4_max_frm_width; 1789 ps_dec_state->u2_horizontal_size = u4_max_frm_width; 1790 1791 ps_dec_state->u2_frame_height = u4_max_frm_height; 1792 ps_dec_state->u2_vertical_size = u4_max_frm_height; 1793 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf; 1794 ps_dec_state->u4_deinterlace = u4_deinterlace; 1795 ps_dec_state->ps_deint_pic = NULL; 1796 } 1797 } 1798 1799 1800 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1801 1802 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 1803 &&((ps_dec_state->u2_vertical_size & 0x1) != 0)) 1804 { 1805 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n"); 1806 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR; 1807 return(IV_FAIL); 1808 1809 1810 } 1811 1812 /* --------------------------------------------------------------------- */ 1813 1814 1815 /* ! */ 1816 // picture buffer manager initialization will be done only for first thread 1817 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr); 1818 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg); 1819 1820 /*************************************************************************/ 1821 /* Internal Frame Buffers */ 1822 /*************************************************************************/ 1823 1824 1825 /* Set first frame to grey */ 1826 { 1827 ps_frm_buf = ps_mem_rec; 1828 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size); 1829 ps_frm_buf++; 1830 } 1831 1832 if(0 == ps_dec_state->u4_share_disp_buf) 1833 { 1834 pic_buf_t *ps_pic_buf; 1835 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base; 1836 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++) 1837 { 1838 UWORD8 *pu1_buf; 1839 pu1_buf = ps_mem_rec->pv_base; 1840 1841 ps_pic_buf->pu1_y = pu1_buf; 1842 pu1_buf += i4_max_ht * i4_max_wd; 1843 1844 ps_pic_buf->pu1_u = pu1_buf; 1845 pu1_buf += i4_max_ht * i4_max_wd >> 2; 1846 1847 ps_pic_buf->pu1_v = pu1_buf; 1848 pu1_buf += i4_max_ht * i4_max_wd >> 2; 1849 1850 ps_pic_buf->i4_buf_id = i; 1851 1852 ps_pic_buf->u1_used_as_ref = 0; 1853 1854 ps_pic_buf->u4_ts = 0; 1855 1856 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i); 1857 ps_mem_rec++; 1858 ps_pic_buf++; 1859 } 1860 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS; 1861 } 1862 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P) 1863 { 1864 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++) 1865 { 1866 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base; 1867 ps_mem_rec++; 1868 } 1869 1870 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS; 1871 } 1872 else 1873 { 1874 ps_mem_rec+=NUM_INT_FRAME_BUFFERS; 1875 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS; 1876 } 1877 1878 1879 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1880 1881 1882 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base; 1883 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size; 1884 u4_num_mem_rec++; 1885 ps_mem_rec++; 1886 1887 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec) 1888 { 1889 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT; 1890 return(IV_FAIL); 1891 1892 } 1893 1894 ps_dec_state->u1_flushfrm = 0; 1895 ps_dec_state->u1_flushcnt = 0; 1896 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size); 1897 1898 1899 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base; 1900 u4_num_mem_rec++; 1901 ps_mem_rec++; 1902 1903 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base; 1904 u4_num_mem_rec++; 1905 ps_mem_rec++; 1906 1907 1908 /*************************************************************************/ 1909 /* Last MemTab is used for storing TabRecords */ 1910 /*************************************************************************/ 1911 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base; 1912 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size); 1913 /* Updating in Decoder Context with memRecords */ 1914 u4_num_mem_rec++; 1915 ps_mem_rec++; 1916 ps_dec_state->u4_num_mem_records = u4_num_mem_rec; 1917 1918 1919 ps_dec_state->u4_num_frames_decoded = 0; 1920 ps_dec_state->aps_ref_pics[0] = NULL; 1921 ps_dec_state->aps_ref_pics[1] = NULL; 1922 1923 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS; 1924 1925 impeg2d_init_arch(ps_dec_state); 1926 1927 impeg2d_init_function_ptr(ps_dec_state); 1928 1929 return(IV_SUCCESS); 1930 } 1931 1932 /*****************************************************************************/ 1933 /* */ 1934 /* Function Name : impeg2d_api_retrieve_mem_rec */ 1935 /* */ 1936 /* Description : */ 1937 /* */ 1938 /* Inputs : */ 1939 /* Globals : <Does it use any global variables?> */ 1940 /* Outputs : */ 1941 /* Returns : void */ 1942 /* */ 1943 /* Issues : none */ 1944 /* */ 1945 /* Revision History: */ 1946 /* */ 1947 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1948 /* 22 10 2008 100356 Draft */ 1949 /* */ 1950 /*****************************************************************************/ 1951 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl, 1952 void *pv_api_ip, 1953 void *pv_api_op) 1954 { 1955 UWORD32 u4_i; 1956 dec_state_t *ps_dec_state; 1957 dec_state_multi_core_t *ps_dec_state_multi_core; 1958 iv_mem_rec_t *ps_mem_rec; 1959 iv_mem_rec_t *ps_temp_rec; 1960 1961 1962 1963 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip; 1964 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op; 1965 1966 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip; 1967 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op; 1968 1969 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location; 1970 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 1971 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1972 ps_temp_rec = ps_dec_state->pv_memTab; 1973 1974 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++) 1975 { 1976 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size; 1977 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment; 1978 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type; 1979 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base; 1980 } 1981 1982 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS; 1983 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records; 1984 1985 impeg2_jobq_deinit(ps_dec_state->pv_jobq); 1986 IMPEG2D_PRINT_STATISTICS(); 1987 1988 1989 return(IV_SUCCESS); 1990 1991 } 1992 1993 /*****************************************************************************/ 1994 /* */ 1995 /* Function Name : impeg2d_api_ctl */ 1996 /* */ 1997 /* Description : */ 1998 /* */ 1999 /* Inputs : */ 2000 /* Globals : <Does it use any global variables?> */ 2001 /* Outputs : */ 2002 /* Returns : void */ 2003 /* */ 2004 /* Issues : none */ 2005 /* */ 2006 /* Revision History: */ 2007 /* */ 2008 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2009 /* 22 10 2008 100356 Draft */ 2010 /* */ 2011 /*****************************************************************************/ 2012 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl, 2013 void *pv_api_ip, 2014 void *pv_api_op) 2015 { 2016 WORD32 i4_sub_cmd; 2017 UWORD32 *pu4_api_ip; 2018 IV_API_CALL_STATUS_T u4_error_code; 2019 2020 pu4_api_ip = (UWORD32 *)pv_api_ip; 2021 i4_sub_cmd = *(pu4_api_ip + 2); 2022 2023 switch(i4_sub_cmd) 2024 { 2025 case IVD_CMD_CTL_GETPARAMS: 2026 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip, 2027 (void *)pv_api_op); 2028 break; 2029 2030 case IVD_CMD_CTL_SETPARAMS: 2031 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip, 2032 (void *)pv_api_op); 2033 break; 2034 2035 case IVD_CMD_CTL_RESET: 2036 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip, 2037 (void *)pv_api_op); 2038 break; 2039 2040 case IVD_CMD_CTL_SETDEFAULT: 2041 u4_error_code = impeg2d_api_set_default(ps_dechdl, 2042 (void *)pv_api_ip, 2043 (void *)pv_api_op); 2044 break; 2045 2046 case IVD_CMD_CTL_FLUSH: 2047 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl, 2048 (void *)pv_api_ip, 2049 (void *)pv_api_op); 2050 break; 2051 2052 case IVD_CMD_CTL_GETBUFINFO: 2053 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl, 2054 (void *)pv_api_ip, 2055 (void *)pv_api_op); 2056 break; 2057 2058 case IVD_CMD_CTL_GETVERSION: 2059 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip, 2060 (void *)pv_api_op); 2061 break; 2062 2063 case IMPEG2D_CMD_CTL_SET_NUM_CORES: 2064 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl, 2065 (void *)pv_api_ip, 2066 (void *)pv_api_op); 2067 break; 2068 2069 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS: 2070 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl, 2071 (void *)pv_api_ip, 2072 (void *)pv_api_op); 2073 break; 2074 2075 case IMPEG2D_CMD_CTL_GET_SEQ_INFO: 2076 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl, 2077 (void *)pv_api_ip, 2078 (void *)pv_api_op); 2079 break; 2080 2081 case IMPEG2D_CMD_CTL_SET_PROCESSOR: 2082 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip, 2083 (void *)pv_api_op); 2084 break; 2085 2086 default: 2087 u4_error_code = IV_FAIL; 2088 break; 2089 } 2090 2091 return (u4_error_code); 2092 2093 } 2094 2095 /*****************************************************************************/ 2096 /* */ 2097 /* Function Name : impeg2d_api_check_struct_sanity */ 2098 /* */ 2099 /* Description : */ 2100 /* */ 2101 /* Inputs : */ 2102 /* Globals : <Does it use any global variables?> */ 2103 /* Outputs : */ 2104 /* Returns : void */ 2105 /* */ 2106 /* Issues : none */ 2107 /* */ 2108 /* Revision History: */ 2109 /* */ 2110 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2111 /* 22 10 2008 100356 Draft */ 2112 /* */ 2113 /*****************************************************************************/ 2114 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle, 2115 void *pv_api_ip, 2116 void *pv_api_op) 2117 { 2118 WORD32 i4_cmd; 2119 UWORD32 *pu4_api_ip; 2120 UWORD32 *pu4_api_op; 2121 WORD32 i,j; 2122 2123 if(NULL == pv_api_op) 2124 return(IV_FAIL); 2125 2126 if(NULL == pv_api_ip) 2127 return(IV_FAIL); 2128 2129 pu4_api_ip = (UWORD32 *)pv_api_ip; 2130 pu4_api_op = (UWORD32 *)pv_api_op; 2131 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1); 2132 2133 /* error checks on handle */ 2134 switch(i4_cmd) 2135 { 2136 case IV_CMD_GET_NUM_MEM_REC: 2137 case IV_CMD_FILL_NUM_MEM_REC: 2138 break; 2139 case IV_CMD_INIT: 2140 if(ps_handle == NULL) 2141 { 2142 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2143 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 2144 return IV_FAIL; 2145 } 2146 2147 if(ps_handle->u4_size != sizeof(iv_obj_t)) 2148 { 2149 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2150 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 2151 return IV_FAIL; 2152 } 2153 break; 2154 case IVD_CMD_GET_DISPLAY_FRAME: 2155 case IVD_CMD_VIDEO_DECODE: 2156 case IV_CMD_RETRIEVE_MEMREC: 2157 case IVD_CMD_SET_DISPLAY_FRAME: 2158 case IVD_CMD_REL_DISPLAY_FRAME: 2159 case IVD_CMD_VIDEO_CTL: 2160 { 2161 if(ps_handle == NULL) 2162 { 2163 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2164 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 2165 return IV_FAIL; 2166 } 2167 2168 if(ps_handle->u4_size != sizeof(iv_obj_t)) 2169 { 2170 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2171 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 2172 return IV_FAIL; 2173 } 2174 if(ps_handle->pv_fxns != impeg2d_api_function) 2175 { 2176 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2177 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 2178 return IV_FAIL; 2179 } 2180 2181 if(ps_handle->pv_codec_handle == NULL) 2182 { 2183 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2184 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 2185 return IV_FAIL; 2186 } 2187 } 2188 break; 2189 default: 2190 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2191 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 2192 return IV_FAIL; 2193 } 2194 2195 switch(i4_cmd) 2196 { 2197 case IV_CMD_GET_NUM_MEM_REC: 2198 { 2199 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip; 2200 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op; 2201 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0; 2202 2203 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t)) 2204 { 2205 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2206 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2207 return(IV_FAIL); 2208 } 2209 2210 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t)) 2211 { 2212 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2213 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2214 return(IV_FAIL); 2215 } 2216 } 2217 break; 2218 case IV_CMD_FILL_NUM_MEM_REC: 2219 { 2220 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip; 2221 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op; 2222 iv_mem_rec_t *ps_mem_rec; 2223 2224 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0; 2225 2226 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t)) 2227 { 2228 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2229 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2230 return(IV_FAIL); 2231 } 2232 2233 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t)) 2234 { 2235 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2236 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2237 return(IV_FAIL); 2238 } 2239 2240 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH) 2241 { 2242 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2243 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 2244 return(IV_FAIL); 2245 } 2246 2247 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH) 2248 { 2249 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2250 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 2251 return(IV_FAIL); 2252 } 2253 2254 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT) 2255 { 2256 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2257 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 2258 return(IV_FAIL); 2259 } 2260 2261 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT) 2262 { 2263 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2264 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 2265 return(IV_FAIL); 2266 } 2267 2268 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location) 2269 { 2270 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2271 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT; 2272 return(IV_FAIL); 2273 } 2274 2275 /* check memrecords sizes are correct */ 2276 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 2277 for(i=0;i<NUM_MEM_RECORDS;i++) 2278 { 2279 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 2280 { 2281 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2282 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 2283 return IV_FAIL; 2284 } 2285 } 2286 } 2287 break; 2288 2289 case IV_CMD_INIT: 2290 { 2291 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip; 2292 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op; 2293 iv_mem_rec_t *ps_mem_rec; 2294 UWORD32 u4_tot_num_mem_recs; 2295 2296 ps_op->s_ivd_init_op_t.u4_error_code = 0; 2297 2298 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t)) 2299 { 2300 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2301 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2302 return(IV_FAIL); 2303 } 2304 2305 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t)) 2306 { 2307 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2308 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2309 return(IV_FAIL); 2310 } 2311 2312 u4_tot_num_mem_recs = NUM_MEM_RECORDS; 2313 2314 2315 2316 2317 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs) 2318 { 2319 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2320 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT; 2321 return(IV_FAIL); 2322 } 2323 2324 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH) 2325 { 2326 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2327 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 2328 return(IV_FAIL); 2329 } 2330 2331 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH) 2332 { 2333 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2334 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 2335 return(IV_FAIL); 2336 } 2337 2338 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT) 2339 { 2340 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2341 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 2342 return(IV_FAIL); 2343 } 2344 2345 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT) 2346 { 2347 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2348 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 2349 return(IV_FAIL); 2350 } 2351 2352 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location) 2353 { 2354 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2355 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT; 2356 return(IV_FAIL); 2357 } 2358 2359 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) && 2360 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU)) 2361 { 2362 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2363 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 2364 return(IV_FAIL); 2365 } 2366 2367 /* verify number of mem records */ 2368 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS) 2369 { 2370 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2371 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT; 2372 return IV_FAIL; 2373 } 2374 2375 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location; 2376 /* verify wether first memrecord is handle or not */ 2377 /* 2378 if(ps_mem_rec->pv_base != ps_handle) 2379 { 2380 // indicate the incorrect handle error 2381 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2382 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE; 2383 return IV_FAIL; 2384 } 2385 */ 2386 /* check memrecords sizes are correct */ 2387 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++) 2388 { 2389 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 2390 { 2391 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2392 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 2393 return IV_FAIL; 2394 } 2395 } 2396 2397 /* verify memtabs for overlapping regions */ 2398 { 2399 UWORD8 *pau1_start[NUM_MEM_RECORDS]; 2400 UWORD8 *pau1_end[NUM_MEM_RECORDS]; 2401 2402 2403 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base); 2404 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1; 2405 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++) 2406 { 2407 /* This array is populated to check memtab overlapp */ 2408 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base); 2409 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1; 2410 2411 for(j = 0; j < i; j++) 2412 { 2413 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j])) 2414 { 2415 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2416 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 2417 return IV_FAIL; 2418 } 2419 2420 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j])) 2421 { 2422 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2423 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 2424 return IV_FAIL; 2425 } 2426 2427 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j])) 2428 { 2429 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2430 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 2431 return IV_FAIL; 2432 } 2433 } 2434 } 2435 } 2436 2437 2438 2439 2440 { 2441 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS]; 2442 2443 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip; 2444 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op; 2445 IV_API_CALL_STATUS_T e_status; 2446 WORD32 i4_num_memrec; 2447 { 2448 2449 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip; 2450 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op; 2451 2452 2453 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t); 2454 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t); 2455 2456 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC; 2457 impeg2d_api_function(NULL, 2458 (void *)&s_no_of_mem_rec_query_ip, 2459 (void *)&s_no_of_mem_rec_query_op); 2460 2461 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec; 2462 2463 2464 2465 } 2466 2467 2468 /* initialize mem records array with sizes */ 2469 for(i = 0; i < i4_num_memrec; i++) 2470 { 2471 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t); 2472 } 2473 2474 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t); 2475 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC; 2476 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd; 2477 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht; 2478 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api; 2479 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf; 2480 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format; 2481 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t); 2482 2483 2484 e_status = impeg2d_api_function(NULL, 2485 (void *)&s_fill_mem_rec_ip, 2486 (void *)&s_fill_mem_rec_op); 2487 if(IV_FAIL == e_status) 2488 { 2489 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code; 2490 return(IV_FAIL); 2491 } 2492 2493 2494 2495 for(i = 0; i < i4_num_memrec; i ++) 2496 { 2497 if(ps_mem_rec[i].pv_base == NULL) 2498 { 2499 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2500 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL; 2501 return IV_FAIL; 2502 } 2503 #ifdef CHECK_ALIGN 2504 2505 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1)) 2506 { 2507 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2508 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR; 2509 return IV_FAIL; 2510 } 2511 #endif //CHECK_ALIGN 2512 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment) 2513 { 2514 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2515 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR; 2516 return IV_FAIL; 2517 } 2518 2519 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size) 2520 { 2521 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2522 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE; 2523 return IV_FAIL; 2524 } 2525 2526 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type) 2527 { 2528 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type) 2529 { 2530 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type) 2531 { 2532 continue; 2533 } 2534 } 2535 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2536 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE; 2537 return IV_FAIL; 2538 } 2539 } 2540 } 2541 2542 2543 } 2544 break; 2545 2546 case IVD_CMD_GET_DISPLAY_FRAME: 2547 { 2548 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip; 2549 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op; 2550 2551 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 2552 2553 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t)) 2554 { 2555 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2556 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2557 return(IV_FAIL); 2558 } 2559 2560 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t)) 2561 { 2562 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2563 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2564 return(IV_FAIL); 2565 } 2566 2567 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0) 2568 { 2569 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2570 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2571 return IV_FAIL; 2572 } 2573 2574 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++) 2575 { 2576 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL) 2577 { 2578 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2579 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 2580 return IV_FAIL; 2581 } 2582 2583 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0) 2584 { 2585 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2586 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2587 return IV_FAIL; 2588 } 2589 /* 2590 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0) 2591 { 2592 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2593 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2594 return IV_FAIL; 2595 } 2596 */ 2597 } 2598 } 2599 break; 2600 case IVD_CMD_REL_DISPLAY_FRAME: 2601 { 2602 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip; 2603 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op; 2604 2605 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 2606 2607 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t)) 2608 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t))) 2609 { 2610 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2611 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2612 return(IV_FAIL); 2613 } 2614 2615 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) && 2616 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t))) 2617 { 2618 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2619 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2620 return(IV_FAIL); 2621 } 2622 2623 } 2624 break; 2625 2626 2627 case IVD_CMD_SET_DISPLAY_FRAME: 2628 { 2629 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip; 2630 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op; 2631 UWORD32 j, i; 2632 2633 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 2634 2635 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t)) 2636 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t))) 2637 { 2638 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2639 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2640 return(IV_FAIL); 2641 } 2642 2643 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) && 2644 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t))) 2645 { 2646 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2647 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2648 return(IV_FAIL); 2649 } 2650 2651 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 2652 { 2653 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2654 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2655 return IV_FAIL; 2656 } 2657 2658 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++) 2659 { 2660 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0) 2661 { 2662 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2663 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2664 return IV_FAIL; 2665 } 2666 2667 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++) 2668 { 2669 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL) 2670 { 2671 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2672 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 2673 return IV_FAIL; 2674 } 2675 2676 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0) 2677 { 2678 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2679 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2680 return IV_FAIL; 2681 } 2682 } 2683 } 2684 } 2685 break; 2686 2687 case IVD_CMD_VIDEO_DECODE: 2688 { 2689 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip; 2690 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op; 2691 2692 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 2693 2694 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t)) 2695 { 2696 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2697 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2698 return(IV_FAIL); 2699 } 2700 2701 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t)) 2702 { 2703 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2704 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2705 return(IV_FAIL); 2706 } 2707 2708 } 2709 break; 2710 2711 case IV_CMD_RETRIEVE_MEMREC: 2712 { 2713 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip; 2714 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op; 2715 iv_mem_rec_t *ps_mem_rec; 2716 2717 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0; 2718 2719 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t)) 2720 { 2721 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2722 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2723 return(IV_FAIL); 2724 } 2725 2726 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t)) 2727 { 2728 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2729 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2730 return(IV_FAIL); 2731 } 2732 2733 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location; 2734 /* check memrecords sizes are correct */ 2735 for(i=0;i < NUM_MEM_RECORDS ; i++) 2736 { 2737 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 2738 { 2739 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2740 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 2741 return IV_FAIL; 2742 } 2743 } 2744 } 2745 break; 2746 2747 case IVD_CMD_VIDEO_CTL: 2748 { 2749 UWORD32 *pu4_ptr_cmd; 2750 UWORD32 u4_sub_command; 2751 2752 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 2753 pu4_ptr_cmd += 2; 2754 u4_sub_command = *pu4_ptr_cmd; 2755 2756 switch(u4_sub_command) 2757 { 2758 case IVD_CMD_CTL_SETPARAMS: 2759 { 2760 impeg2d_ctl_set_config_ip_t *ps_ip; 2761 impeg2d_ctl_set_config_op_t *ps_op; 2762 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip; 2763 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op; 2764 2765 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0; 2766 2767 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t)) 2768 { 2769 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2770 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2771 return IV_FAIL; 2772 } 2773 } 2774 case IVD_CMD_CTL_SETDEFAULT: 2775 { 2776 impeg2d_ctl_set_config_op_t *ps_op; 2777 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op; 2778 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0; 2779 2780 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t)) 2781 { 2782 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2783 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2784 return IV_FAIL; 2785 } 2786 } 2787 break; 2788 2789 case IVD_CMD_CTL_GETPARAMS: 2790 { 2791 impeg2d_ctl_getstatus_ip_t *ps_ip; 2792 impeg2d_ctl_getstatus_op_t *ps_op; 2793 2794 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip; 2795 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op; 2796 2797 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0; 2798 2799 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t)) 2800 { 2801 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2802 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2803 return IV_FAIL; 2804 } 2805 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t)) 2806 { 2807 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2808 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2809 return IV_FAIL; 2810 } 2811 } 2812 break; 2813 2814 case IVD_CMD_CTL_GETBUFINFO: 2815 { 2816 impeg2d_ctl_getbufinfo_ip_t *ps_ip; 2817 impeg2d_ctl_getbufinfo_op_t *ps_op; 2818 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip; 2819 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op; 2820 2821 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0; 2822 2823 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t)) 2824 { 2825 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2826 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2827 return IV_FAIL; 2828 } 2829 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t)) 2830 { 2831 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2832 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2833 return IV_FAIL; 2834 } 2835 } 2836 break; 2837 2838 case IVD_CMD_CTL_GETVERSION: 2839 { 2840 impeg2d_ctl_getversioninfo_ip_t *ps_ip; 2841 impeg2d_ctl_getversioninfo_op_t *ps_op; 2842 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip; 2843 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op; 2844 2845 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0; 2846 2847 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t)) 2848 { 2849 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2850 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2851 return IV_FAIL; 2852 } 2853 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t)) 2854 { 2855 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2856 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2857 return IV_FAIL; 2858 } 2859 } 2860 break; 2861 2862 case IVD_CMD_CTL_FLUSH: 2863 { 2864 impeg2d_ctl_flush_ip_t *ps_ip; 2865 impeg2d_ctl_flush_op_t *ps_op; 2866 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip; 2867 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op; 2868 2869 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0; 2870 2871 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t)) 2872 { 2873 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2874 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2875 return IV_FAIL; 2876 } 2877 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t)) 2878 { 2879 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2880 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2881 return IV_FAIL; 2882 } 2883 } 2884 break; 2885 2886 case IVD_CMD_CTL_RESET: 2887 { 2888 impeg2d_ctl_reset_ip_t *ps_ip; 2889 impeg2d_ctl_reset_op_t *ps_op; 2890 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip; 2891 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op; 2892 2893 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0; 2894 2895 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t)) 2896 { 2897 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2898 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2899 return IV_FAIL; 2900 } 2901 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t)) 2902 { 2903 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2904 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2905 return IV_FAIL; 2906 } 2907 } 2908 break; 2909 2910 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS: 2911 { 2912 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip; 2913 impeg2d_ctl_get_frame_dimensions_op_t *ps_op; 2914 2915 ps_ip = 2916 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 2917 ps_op = 2918 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op; 2919 2920 if(ps_ip->u4_size 2921 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t)) 2922 { 2923 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2924 ps_op->u4_error_code |= 2925 IVD_IP_API_STRUCT_SIZE_INCORRECT; 2926 return IV_FAIL; 2927 } 2928 2929 if(ps_op->u4_size 2930 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t)) 2931 { 2932 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2933 ps_op->u4_error_code |= 2934 IVD_OP_API_STRUCT_SIZE_INCORRECT; 2935 return IV_FAIL; 2936 } 2937 2938 break; 2939 } 2940 case IMPEG2D_CMD_CTL_GET_SEQ_INFO: 2941 { 2942 impeg2d_ctl_get_seq_info_ip_t *ps_ip; 2943 impeg2d_ctl_get_seq_info_op_t *ps_op; 2944 2945 ps_ip = 2946 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip; 2947 ps_op = 2948 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op; 2949 2950 if(ps_ip->u4_size 2951 != sizeof(impeg2d_ctl_get_seq_info_ip_t)) 2952 { 2953 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2954 ps_op->u4_error_code |= 2955 IVD_IP_API_STRUCT_SIZE_INCORRECT; 2956 return IV_FAIL; 2957 } 2958 2959 if(ps_op->u4_size 2960 != sizeof(impeg2d_ctl_get_seq_info_op_t)) 2961 { 2962 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2963 ps_op->u4_error_code |= 2964 IVD_OP_API_STRUCT_SIZE_INCORRECT; 2965 return IV_FAIL; 2966 } 2967 2968 break; 2969 } 2970 case IMPEG2D_CMD_CTL_SET_NUM_CORES: 2971 { 2972 impeg2d_ctl_set_num_cores_ip_t *ps_ip; 2973 impeg2d_ctl_set_num_cores_op_t *ps_op; 2974 2975 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip; 2976 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op; 2977 2978 if(ps_ip->u4_size 2979 != sizeof(impeg2d_ctl_set_num_cores_ip_t)) 2980 { 2981 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2982 ps_op->u4_error_code |= 2983 IVD_IP_API_STRUCT_SIZE_INCORRECT; 2984 return IV_FAIL; 2985 } 2986 2987 if(ps_op->u4_size 2988 != sizeof(impeg2d_ctl_set_num_cores_op_t)) 2989 { 2990 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2991 ps_op->u4_error_code |= 2992 IVD_OP_API_STRUCT_SIZE_INCORRECT; 2993 return IV_FAIL; 2994 } 2995 2996 #ifdef MULTICORE 2997 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS)) 2998 #else 2999 if(ps_ip->u4_num_cores != 1) 3000 #endif 3001 { 3002 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3003 return IV_FAIL; 3004 } 3005 break; 3006 } 3007 case IMPEG2D_CMD_CTL_SET_PROCESSOR: 3008 { 3009 impeg2d_ctl_set_processor_ip_t *ps_ip; 3010 impeg2d_ctl_set_processor_op_t *ps_op; 3011 3012 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip; 3013 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op; 3014 3015 if(ps_ip->u4_size 3016 != sizeof(impeg2d_ctl_set_processor_ip_t)) 3017 { 3018 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3019 ps_op->u4_error_code |= 3020 IVD_IP_API_STRUCT_SIZE_INCORRECT; 3021 return IV_FAIL; 3022 } 3023 3024 if(ps_op->u4_size 3025 != sizeof(impeg2d_ctl_set_processor_op_t)) 3026 { 3027 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3028 ps_op->u4_error_code |= 3029 IVD_OP_API_STRUCT_SIZE_INCORRECT; 3030 return IV_FAIL; 3031 } 3032 3033 break; 3034 } 3035 default: 3036 break; 3037 3038 } 3039 } 3040 break; 3041 3042 default: 3043 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 3044 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 3045 return IV_FAIL; 3046 } 3047 3048 3049 } 3050 3051 return IV_SUCCESS; 3052 } 3053 3054 /*****************************************************************************/ 3055 /* */ 3056 /* Function Name : impeg2d_api_entity */ 3057 /* */ 3058 /* Description : */ 3059 /* */ 3060 /* Inputs : */ 3061 /* Globals : <Does it use any global variables?> */ 3062 /* Outputs : */ 3063 /* Returns : void */ 3064 /* */ 3065 /* Issues : none */ 3066 /* */ 3067 /* Revision History: */ 3068 /* */ 3069 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3070 /* 22 10 2008 100356 Draft */ 3071 /* */ 3072 /*****************************************************************************/ 3073 3074 3075 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl, 3076 void *pv_api_ip, 3077 void *pv_api_op) 3078 { 3079 iv_obj_t *ps_dec_handle; 3080 dec_state_t *ps_dec_state; 3081 dec_state_multi_core_t *ps_dec_state_multi_core; 3082 3083 impeg2d_video_decode_ip_t *ps_dec_ip; 3084 3085 impeg2d_video_decode_op_t *ps_dec_op; 3086 WORD32 bytes_remaining; 3087 pic_buf_t *ps_disp_pic; 3088 3089 3090 3091 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip; 3092 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op; 3093 3094 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t)); 3095 3096 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t); 3097 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0; 3098 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes; 3099 3100 ps_dec_handle = (iv_obj_t *)ps_dechdl; 3101 3102 if(ps_dechdl == NULL) 3103 { 3104 return(IV_FAIL); 3105 } 3106 3107 3108 3109 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle; 3110 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 3111 3112 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3113 if(0 == ps_dec_state->u4_share_disp_buf) 3114 { 3115 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0]; 3116 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1]; 3117 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2]; 3118 } 3119 3120 ps_dec_state->ps_disp_pic = NULL; 3121 ps_dec_state->i4_frame_decoded = 0; 3122 /*rest bytes consumed */ 3123 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0; 3124 3125 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS; 3126 3127 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0)) 3128 { 3129 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3130 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 3131 return IV_FAIL; 3132 } 3133 3134 3135 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT) 3136 { 3137 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR; 3138 return(IV_FAIL); 3139 } 3140 3141 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0)) 3142 { 3143 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op); 3144 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed; 3145 } 3146 3147 if((1 != ps_dec_state->u2_decode_header) && 3148 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm)) 3149 { 3150 if(ps_dec_state->u1_flushfrm) 3151 { 3152 if(ps_dec_state->aps_ref_pics[1] != NULL) 3153 { 3154 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id); 3155 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF); 3156 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF); 3157 3158 ps_dec_state->aps_ref_pics[1] = NULL; 3159 ps_dec_state->aps_ref_pics[0] = NULL; 3160 3161 } 3162 else if(ps_dec_state->aps_ref_pics[0] != NULL) 3163 { 3164 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id); 3165 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF); 3166 3167 ps_dec_state->aps_ref_pics[0] = NULL; 3168 } 3169 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t); 3170 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t); 3171 3172 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id); 3173 3174 ps_dec_state->ps_disp_pic = ps_disp_pic; 3175 if(ps_disp_pic == NULL) 3176 { 3177 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0; 3178 } 3179 else 3180 { 3181 WORD32 fmt_conv; 3182 if(0 == ps_dec_state->u4_share_disp_buf) 3183 { 3184 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0]; 3185 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1]; 3186 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2]; 3187 fmt_conv = 1; 3188 } 3189 else 3190 { 3191 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y; 3192 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat) 3193 { 3194 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u; 3195 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v; 3196 fmt_conv = 0; 3197 } 3198 else 3199 { 3200 UWORD8 *pu1_buf; 3201 3202 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1]; 3203 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf; 3204 3205 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2]; 3206 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf; 3207 fmt_conv = 1; 3208 } 3209 } 3210 3211 if(fmt_conv == 1) 3212 { 3213 iv_yuv_buf_t *ps_dst; 3214 3215 3216 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3217 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame)) 3218 { 3219 impeg2d_deinterlace(ps_dec_state, 3220 ps_disp_pic, 3221 ps_dst, 3222 0, 3223 ps_dec_state->u2_vertical_size); 3224 3225 } 3226 else 3227 { 3228 impeg2d_format_convert(ps_dec_state, 3229 ps_disp_pic, 3230 ps_dst, 3231 0, 3232 ps_dec_state->u2_vertical_size); 3233 } 3234 } 3235 3236 if(ps_dec_state->u4_deinterlace) 3237 { 3238 if(ps_dec_state->ps_deint_pic) 3239 { 3240 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, 3241 ps_dec_state->ps_deint_pic->i4_buf_id, 3242 MPEG2_BUF_MGR_DEINT); 3243 } 3244 ps_dec_state->ps_deint_pic = ps_disp_pic; 3245 } 3246 if(0 == ps_dec_state->u4_share_disp_buf) 3247 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP); 3248 3249 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size; 3250 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size; 3251 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1; 3252 3253 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id; 3254 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts; 3255 3256 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat; 3257 3258 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type); 3259 3260 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE; 3261 3262 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size; 3263 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride; 3264 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size; 3265 3266 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1; 3267 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3268 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1; 3269 3270 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1; 3271 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3272 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1; 3273 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3274 3275 switch(ps_dec_state->i4_chromaFormat) 3276 { 3277 case IV_YUV_420SP_UV: 3278 case IV_YUV_420SP_VU: 3279 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size; 3280 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride; 3281 break; 3282 case IV_YUV_422ILE: 3283 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0; 3284 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0; 3285 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0; 3286 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0; 3287 break; 3288 default: 3289 break; 3290 } 3291 3292 3293 } 3294 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present) 3295 { 3296 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present) 3297 { 3298 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0], 3299 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1], 3300 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2], 3301 ps_dec_state->u4_frm_buf_stride, 3302 ps_dec_state->u2_horizontal_size, 3303 ps_dec_state->u2_vertical_size, 3304 ps_dec_state->i4_chromaFormat, 3305 ps_dec_state->u2_horizontal_size, 3306 ps_dec_state->u2_vertical_size); 3307 } 3308 return(IV_SUCCESS); 3309 } 3310 else 3311 { 3312 ps_dec_state->u1_flushfrm = 0; 3313 3314 return(IV_FAIL); 3315 } 3316 3317 } 3318 else if(ps_dec_state->u1_flushfrm==0) 3319 { 3320 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t); 3321 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t); 3322 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4) 3323 { 3324 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes; 3325 return(IV_FAIL); 3326 } 3327 3328 if(1 == ps_dec_state->u4_share_disp_buf) 3329 { 3330 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg)) 3331 { 3332 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = 3333 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL; 3334 return IV_FAIL; 3335 } 3336 } 3337 3338 3339 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat; 3340 3341 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type); 3342 3343 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE; 3344 3345 if (0 == ps_dec_state->u4_frm_buf_stride) 3346 { 3347 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size); 3348 } 3349 3350 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size; 3351 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride; 3352 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size; 3353 3354 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1; 3355 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3356 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1; 3357 3358 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1; 3359 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3360 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1; 3361 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3362 3363 switch(ps_dec_state->i4_chromaFormat) 3364 { 3365 case IV_YUV_420SP_UV: 3366 case IV_YUV_420SP_VU: 3367 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size; 3368 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride; 3369 break; 3370 case IV_YUV_422ILE: 3371 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0; 3372 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0; 3373 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0; 3374 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0; 3375 break; 3376 default: 3377 break; 3378 } 3379 3380 if( ps_dec_state->u1_flushfrm == 0) 3381 { 3382 ps_dec_state->u1_flushcnt = 0; 3383 3384 /*************************************************************************/ 3385 /* Frame Decode */ 3386 /*************************************************************************/ 3387 3388 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op); 3389 3390 if (IVD_ERROR_NONE == 3391 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code) 3392 { 3393 if(ps_dec_state->u1_first_frame_done == 0) 3394 { 3395 ps_dec_state->u1_first_frame_done = 1; 3396 } 3397 3398 if(ps_dec_state->ps_disp_pic) 3399 { 3400 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1; 3401 switch(ps_dec_state->ps_disp_pic->e_pic_type) 3402 { 3403 case I_PIC : 3404 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME; 3405 break; 3406 3407 case P_PIC: 3408 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME; 3409 break; 3410 3411 case B_PIC: 3412 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME; 3413 break; 3414 3415 case D_PIC: 3416 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME; 3417 break; 3418 3419 default : 3420 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT; 3421 break; 3422 } 3423 } 3424 else 3425 { 3426 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0; 3427 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME; 3428 } 3429 3430 ps_dec_state->u4_num_frames_decoded++; 3431 } 3432 } 3433 else 3434 { 3435 ps_dec_state->u1_flushcnt++; 3436 } 3437 } 3438 if(ps_dec_state->ps_disp_pic) 3439 { 3440 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id; 3441 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts; 3442 3443 if(0 == ps_dec_state->u4_share_disp_buf) 3444 { 3445 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP); 3446 } 3447 } 3448 3449 if(ps_dec_state->u4_deinterlace) 3450 { 3451 if(ps_dec_state->ps_deint_pic) 3452 { 3453 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, 3454 ps_dec_state->ps_deint_pic->i4_buf_id, 3455 MPEG2_BUF_MGR_DEINT); 3456 } 3457 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic; 3458 } 3459 3460 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present) 3461 { 3462 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0], 3463 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1], 3464 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2], 3465 ps_dec_state->u4_frm_buf_stride, 3466 ps_dec_state->u2_horizontal_size, 3467 ps_dec_state->u2_vertical_size, 3468 ps_dec_state->i4_chromaFormat, 3469 ps_dec_state->u2_horizontal_size, 3470 ps_dec_state->u2_vertical_size); 3471 } 3472 3473 } 3474 3475 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1; 3476 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type; 3477 3478 3479 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code) 3480 return IV_FAIL; 3481 else 3482 return IV_SUCCESS; 3483 } 3484
