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      1 //===-- VIInstructions.td - VI Instruction Defintions ---------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 // Instruction definitions for VI and newer.
     10 //===----------------------------------------------------------------------===//
     11 
     12 let SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI in {
     13 
     14 let DisableSIDecoder = 1 in {
     15 
     16 //===----------------------------------------------------------------------===//
     17 // VOP1 Instructions
     18 //===----------------------------------------------------------------------===//
     19 
     20 defm V_CVT_F16_U16 : VOP1Inst <vop1<0, 0x39>, "v_cvt_f16_u16", VOP_F16_I16>;
     21 defm V_CVT_F16_I16 : VOP1Inst <vop1<0, 0x3a>, "v_cvt_f16_i16", VOP_F16_I16>;
     22 defm V_CVT_U16_F16 : VOP1Inst <vop1<0, 0x3b>, "v_cvt_u16_f16", VOP_I16_F16>;
     23 defm V_CVT_I16_F16 : VOP1Inst <vop1<0, 0x3c>, "v_cvt_i16_f16", VOP_I16_F16>;
     24 defm V_RCP_F16 : VOP1Inst <vop1<0, 0x3d>, "v_rcp_f16", VOP_F16_F16>;
     25 defm V_SQRT_F16 : VOP1Inst <vop1<0, 0x3e>, "v_sqrt_f16", VOP_F16_F16>;
     26 defm V_RSQ_F16 : VOP1Inst <vop1<0, 0x3f>, "v_rsq_f16", VOP_F16_F16>;
     27 defm V_LOG_F16 : VOP1Inst <vop1<0, 0x40>, "v_log_f16", VOP_F16_F16>;
     28 defm V_EXP_F16 : VOP1Inst <vop1<0, 0x41>, "v_exp_f16", VOP_F16_F16>;
     29 defm V_FREXP_MANT_F16 : VOP1Inst <vop1<0, 0x42>, "v_frexp_mant_f16",
     30   VOP_F16_F16
     31 >;
     32 defm V_FREXP_EXP_I16_F16 : VOP1Inst <vop1<0, 0x43>, "v_frexp_exp_i16_f16",
     33   VOP_I16_F16
     34 >;
     35 defm V_FLOOR_F16 : VOP1Inst <vop1<0, 0x44>, "v_floor_f16", VOP_F16_F16>;
     36 defm V_CEIL_F16 : VOP1Inst <vop1<0, 0x45>, "v_ceil_f16", VOP_F16_F16>;
     37 defm V_TRUNC_F16 : VOP1Inst <vop1<0, 0x46>, "v_trunc_f16", VOP_F16_F16>;
     38 defm V_RNDNE_F16 : VOP1Inst <vop1<0, 0x47>, "v_rndne_f16", VOP_F16_F16>;
     39 defm V_FRACT_F16 : VOP1Inst <vop1<0, 0x48>, "v_fract_f16", VOP_F16_F16>;
     40 defm V_SIN_F16 : VOP1Inst <vop1<0, 0x49>, "v_sin_f16", VOP_F16_F16>;
     41 defm V_COS_F16 : VOP1Inst <vop1<0, 0x4a>, "v_cos_f16", VOP_F16_F16>;
     42 
     43 //===----------------------------------------------------------------------===//
     44 // VOP2 Instructions
     45 //===----------------------------------------------------------------------===//
     46 
     47 let isCommutable = 1 in {
     48 
     49 defm V_ADD_F16 : VOP2Inst <vop2<0, 0x1f>, "v_add_f16", VOP_F16_F16_F16>;
     50 defm V_SUB_F16 : VOP2Inst <vop2<0, 0x20>, "v_sub_f16", VOP_F16_F16_F16>;
     51 defm V_SUBREV_F16 : VOP2Inst <vop2<0, 0x21>, "v_subrev_f16", VOP_F16_F16_F16,
     52   null_frag, "v_sub_f16"
     53 >;
     54 defm V_MUL_F16 : VOP2Inst <vop2<0, 0x22>, "v_mul_f16", VOP_F16_F16_F16>;
     55 defm V_MAC_F16 : VOP2Inst <vop2<0, 0x23>, "v_mac_f16", VOP_F16_F16_F16>;
     56 } // End isCommutable = 1
     57 defm V_MADMK_F16 : VOP2MADK <vop2<0,0x24>, "v_madmk_f16", VOP_MADMK>;
     58 let isCommutable = 1 in {
     59 defm V_MADAK_F16 : VOP2MADK <vop2<0,0x25>, "v_madak_f16", VOP_MADAK>;
     60 defm V_ADD_U16 : VOP2Inst <vop2<0,0x26>, "v_add_u16", VOP_I16_I16_I16>;
     61 defm V_SUB_U16 : VOP2Inst <vop2<0,0x27>, "v_sub_u16" , VOP_I16_I16_I16>;
     62 defm V_SUBREV_U16 : VOP2Inst <vop2<0,0x28>, "v_subrev_u16", VOP_I16_I16_I16>;
     63 defm V_MUL_LO_U16 : VOP2Inst <vop2<0,0x29>, "v_mul_lo_u16", VOP_I16_I16_I16>;
     64 } // End isCommutable = 1
     65 defm V_LSHLREV_B16 : VOP2Inst <vop2<0,0x2a>, "v_lshlrev_b16", VOP_I16_I16_I16>;
     66 defm V_LSHRREV_B16 : VOP2Inst <vop2<0,0x2b>, "v_lshrrev_b16", VOP_I16_I16_I16>;
     67 defm V_ASHRREV_B16 : VOP2Inst <vop2<0,0x2c>, "v_ashrrev_b16", VOP_I16_I16_I16>;
     68 let isCommutable = 1 in {
     69 defm V_MAX_F16 : VOP2Inst <vop2<0,0x2d>, "v_max_f16", VOP_F16_F16_F16>;
     70 defm V_MIN_F16 : VOP2Inst <vop2<0,0x2e>, "v_min_f16", VOP_F16_F16_F16>;
     71 defm V_MAX_U16 : VOP2Inst <vop2<0,0x2f>, "v_max_u16", VOP_I16_I16_I16>;
     72 defm V_MAX_I16 : VOP2Inst <vop2<0,0x30>, "v_max_i16", VOP_I16_I16_I16>;
     73 defm V_MIN_U16 : VOP2Inst <vop2<0,0x31>, "v_min_u16", VOP_I16_I16_I16>;
     74 defm V_MIN_I16 : VOP2Inst <vop2<0,0x32>, "v_min_i16", VOP_I16_I16_I16>;
     75 } // End isCommutable = 1
     76 defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16", VOP_F16_F16_I16>;
     77 
     78 //===----------------------------------------------------------------------===//
     79 // VOP3 Instructions
     80 //===----------------------------------------------------------------------===//
     81 let isCommutable = 1 in {
     82     defm V_MAD_F16 : VOP3Inst <vop3<0, 0x1ea>, "v_mad_f16", VOP_F16_F16_F16_F16>;
     83     defm V_MAD_U16 : VOP3Inst <vop3<0, 0x1eb>, "v_mad_u16", VOP_I16_I16_I16_I16>;
     84     defm V_MAD_I16 : VOP3Inst <vop3<0, 0x1ec>, "v_mad_i16", VOP_I16_I16_I16_I16>;
     85 }
     86 } // let DisableSIDecoder = 1
     87 
     88 // Aliases to simplify matching of floating-point instructions that
     89 // are VOP2 on SI and VOP3 on VI.
     90 
     91 class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
     92   name#" $dst, $src0, $src1",
     93   (inst VGPR_32:$dst, 0, VCSrc_32:$src0, 0, VCSrc_32:$src1, 0, 0)
     94 >, PredicateControl {
     95   let UseInstAsmMatchConverter = 0;
     96 }
     97 
     98 def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
     99 def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
    100 def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
    101 def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
    102 def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
    103 
    104 //===----------------------------------------------------------------------===//
    105 // SMEM Instructions
    106 //===----------------------------------------------------------------------===//
    107 
    108 def S_DCACHE_WB : SMEM_Inval <0x21,
    109   "s_dcache_wb", int_amdgcn_s_dcache_wb>;
    110 
    111 def S_DCACHE_WB_VOL : SMEM_Inval <0x23,
    112   "s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
    113 
    114 def S_MEMREALTIME : SMEM_Ret<0x25,
    115   "s_memrealtime", int_amdgcn_s_memrealtime>;
    116 
    117 } // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI
    118 
    119 let Predicates = [isVI] in {
    120 
    121 // 1. Offset as 20bit DWORD immediate
    122 def : Pat <
    123   (SIload_constant v4i32:$sbase, IMM20bit:$offset),
    124   (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
    125 >;
    126 
    127 //===----------------------------------------------------------------------===//
    128 // DPP Patterns
    129 //===----------------------------------------------------------------------===//
    130 
    131 def : Pat <
    132   (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
    133                       imm:$bound_ctrl),
    134   (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask),
    135                        (as_i32imm $bank_mask), (as_i1imm $bound_ctrl))
    136 >;
    137 
    138 //===----------------------------------------------------------------------===//
    139 // Misc Patterns
    140 //===----------------------------------------------------------------------===//
    141 
    142 def : Pat <
    143   (i64 (readcyclecounter)),
    144   (S_MEMREALTIME)
    145 >;
    146 
    147 //===----------------------------------------------------------------------===//
    148 // DS_PERMUTE/DS_BPERMUTE Instructions.
    149 //===----------------------------------------------------------------------===//
    150 
    151 let Uses = [EXEC] in {
    152 defm DS_PERMUTE_B32 : DS_1A1D_PERMUTE <0x3e, "ds_permute_b32", VGPR_32,
    153                                        int_amdgcn_ds_permute>;
    154 defm DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <0x3f, "ds_bpermute_b32", VGPR_32,
    155                                        int_amdgcn_ds_bpermute>;
    156 }
    157 
    158 } // End Predicates = [isVI]
    159