Home | History | Annotate | Download | only in ARM 
      1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the ARM specific subclass of TargetMachine.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
     15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
     16 
     17 #include "ARMInstrInfo.h"
     18 #include "ARMSubtarget.h"
     19 #include "llvm/IR/DataLayout.h"
     20 #include "llvm/Target/TargetMachine.h"
     21 
     22 namespace llvm {
     23 
     24 class ARMBaseTargetMachine : public LLVMTargetMachine {
     25 public:
     26   enum ARMABI {
     27     ARM_ABI_UNKNOWN,
     28     ARM_ABI_APCS,
     29     ARM_ABI_AAPCS, // ARM EABI
     30     ARM_ABI_AAPCS16
     31   } TargetABI;
     32 
     33 protected:
     34   std::unique_ptr<TargetLoweringObjectFile> TLOF;
     35   ARMSubtarget        Subtarget;
     36   bool isLittle;
     37   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
     38 
     39 public:
     40   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
     41                        StringRef FS, const TargetOptions &Options,
     42                        Optional<Reloc::Model> RM, CodeModel::Model CM,
     43                        CodeGenOpt::Level OL, bool isLittle);
     44   ~ARMBaseTargetMachine() override;
     45 
     46   const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
     47   const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
     48   bool isLittleEndian() const { return isLittle; }
     49 
     50   /// \brief Get the TargetIRAnalysis for this target.
     51   TargetIRAnalysis getTargetIRAnalysis() override;
     52 
     53   // Pass Pipeline Configuration
     54   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
     55 
     56   TargetLoweringObjectFile *getObjFileLowering() const override {
     57     return TLOF.get();
     58   }
     59 };
     60 
     61 /// ARM target machine.
     62 ///
     63 class ARMTargetMachine : public ARMBaseTargetMachine {
     64   virtual void anchor();
     65  public:
     66    ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
     67                     StringRef FS, const TargetOptions &Options,
     68                     Optional<Reloc::Model> RM, CodeModel::Model CM,
     69                     CodeGenOpt::Level OL, bool isLittle);
     70 };
     71 
     72 /// ARM little endian target machine.
     73 ///
     74 class ARMLETargetMachine : public ARMTargetMachine {
     75   void anchor() override;
     76 public:
     77   ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
     78                      StringRef FS, const TargetOptions &Options,
     79                      Optional<Reloc::Model> RM, CodeModel::Model CM,
     80                      CodeGenOpt::Level OL);
     81 };
     82 
     83 /// ARM big endian target machine.
     84 ///
     85 class ARMBETargetMachine : public ARMTargetMachine {
     86   void anchor() override;
     87 public:
     88   ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
     89                      StringRef FS, const TargetOptions &Options,
     90                      Optional<Reloc::Model> RM, CodeModel::Model CM,
     91                      CodeGenOpt::Level OL);
     92 };
     93 
     94 /// Thumb target machine.
     95 /// Due to the way architectures are handled, this represents both
     96 ///   Thumb-1 and Thumb-2.
     97 ///
     98 class ThumbTargetMachine : public ARMBaseTargetMachine {
     99   virtual void anchor();
    100 public:
    101   ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
    102                      StringRef FS, const TargetOptions &Options,
    103                      Optional<Reloc::Model> RM, CodeModel::Model CM,
    104                      CodeGenOpt::Level OL, bool isLittle);
    105 };
    106 
    107 /// Thumb little endian target machine.
    108 ///
    109 class ThumbLETargetMachine : public ThumbTargetMachine {
    110   void anchor() override;
    111 public:
    112   ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
    113                        StringRef FS, const TargetOptions &Options,
    114                        Optional<Reloc::Model> RM, CodeModel::Model CM,
    115                        CodeGenOpt::Level OL);
    116 };
    117 
    118 /// Thumb big endian target machine.
    119 ///
    120 class ThumbBETargetMachine : public ThumbTargetMachine {
    121   void anchor() override;
    122 public:
    123   ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
    124                        StringRef FS, const TargetOptions &Options,
    125                        Optional<Reloc::Model> RM, CodeModel::Model CM,
    126                        CodeGenOpt::Level OL);
    127 };
    128 
    129 } // end namespace llvm
    130 
    131 #endif
    132