1 //===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class prints an Sparc MCInst to a .s file. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SparcInstPrinter.h" 15 #include "Sparc.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCRegisterInfo.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/MC/MCSymbol.h" 21 #include "llvm/Support/raw_ostream.h" 22 using namespace llvm; 23 24 #define DEBUG_TYPE "asm-printer" 25 26 // The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target 27 // namespace. But SPARC backend uses "SP" as its namespace. 28 namespace llvm { 29 namespace Sparc { 30 using namespace SP; 31 } 32 } 33 34 #define GET_INSTRUCTION_NAME 35 #define PRINT_ALIAS_INSTR 36 #include "SparcGenAsmWriter.inc" 37 38 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { 39 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; 40 } 41 42 void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const 43 { 44 OS << '%' << StringRef(getRegisterName(RegNo)).lower(); 45 } 46 47 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 48 StringRef Annot, const MCSubtargetInfo &STI) { 49 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) 50 printInstruction(MI, STI, O); 51 printAnnotation(O, Annot); 52 } 53 54 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, 55 const MCSubtargetInfo &STI, 56 raw_ostream &O) { 57 switch (MI->getOpcode()) { 58 default: return false; 59 case SP::JMPLrr: 60 case SP::JMPLri: { 61 if (MI->getNumOperands() != 3) 62 return false; 63 if (!MI->getOperand(0).isReg()) 64 return false; 65 switch (MI->getOperand(0).getReg()) { 66 default: return false; 67 case SP::G0: // jmp $addr | ret | retl 68 if (MI->getOperand(2).isImm() && 69 MI->getOperand(2).getImm() == 8) { 70 switch(MI->getOperand(1).getReg()) { 71 default: break; 72 case SP::I7: O << "\tret"; return true; 73 case SP::O7: O << "\tretl"; return true; 74 } 75 } 76 O << "\tjmp "; printMemOperand(MI, 1, STI, O); 77 return true; 78 case SP::O7: // call $addr 79 O << "\tcall "; printMemOperand(MI, 1, STI, O); 80 return true; 81 } 82 } 83 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: 84 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { 85 if (isV9(STI) 86 || (MI->getNumOperands() != 3) 87 || (!MI->getOperand(0).isReg()) 88 || (MI->getOperand(0).getReg() != SP::FCC0)) 89 return false; 90 // if V8, skip printing %fcc0. 91 switch(MI->getOpcode()) { 92 default: 93 case SP::V9FCMPS: O << "\tfcmps "; break; 94 case SP::V9FCMPD: O << "\tfcmpd "; break; 95 case SP::V9FCMPQ: O << "\tfcmpq "; break; 96 case SP::V9FCMPES: O << "\tfcmpes "; break; 97 case SP::V9FCMPED: O << "\tfcmped "; break; 98 case SP::V9FCMPEQ: O << "\tfcmpeq "; break; 99 } 100 printOperand(MI, 1, STI, O); 101 O << ", "; 102 printOperand(MI, 2, STI, O); 103 return true; 104 } 105 } 106 } 107 108 void SparcInstPrinter::printOperand(const MCInst *MI, int opNum, 109 const MCSubtargetInfo &STI, 110 raw_ostream &O) { 111 const MCOperand &MO = MI->getOperand (opNum); 112 113 if (MO.isReg()) { 114 printRegName(O, MO.getReg()); 115 return ; 116 } 117 118 if (MO.isImm()) { 119 switch (MI->getOpcode()) { 120 default: 121 O << (int)MO.getImm(); 122 return; 123 124 case SP::TICCri: // Fall through 125 case SP::TICCrr: // Fall through 126 case SP::TRAPri: // Fall through 127 case SP::TRAPrr: // Fall through 128 case SP::TXCCri: // Fall through 129 case SP::TXCCrr: // Fall through 130 // Only seven-bit values up to 127. 131 O << ((int) MO.getImm() & 0x7f); 132 return; 133 } 134 } 135 136 assert(MO.isExpr() && "Unknown operand kind in printOperand"); 137 MO.getExpr()->print(O, &MAI); 138 } 139 140 void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum, 141 const MCSubtargetInfo &STI, 142 raw_ostream &O, const char *Modifier) { 143 printOperand(MI, opNum, STI, O); 144 145 // If this is an ADD operand, emit it like normal operands. 146 if (Modifier && !strcmp(Modifier, "arith")) { 147 O << ", "; 148 printOperand(MI, opNum+1, STI, O); 149 return; 150 } 151 const MCOperand &MO = MI->getOperand(opNum+1); 152 153 if (MO.isReg() && MO.getReg() == SP::G0) 154 return; // don't print "+%g0" 155 if (MO.isImm() && MO.getImm() == 0) 156 return; // don't print "+0" 157 158 O << "+"; 159 160 printOperand(MI, opNum+1, STI, O); 161 } 162 163 void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum, 164 const MCSubtargetInfo &STI, 165 raw_ostream &O) { 166 int CC = (int)MI->getOperand(opNum).getImm(); 167 switch (MI->getOpcode()) { 168 default: break; 169 case SP::FBCOND: 170 case SP::FBCONDA: 171 case SP::BPFCC: 172 case SP::BPFCCA: 173 case SP::BPFCCNT: 174 case SP::BPFCCANT: 175 case SP::MOVFCCrr: case SP::V9MOVFCCrr: 176 case SP::MOVFCCri: case SP::V9MOVFCCri: 177 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC: 178 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC: 179 case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC: 180 // Make sure CC is a fp conditional flag. 181 CC = (CC < 16) ? (CC + 16) : CC; 182 break; 183 case SP::CBCOND: 184 case SP::CBCONDA: 185 // Make sure CC is a cp conditional flag. 186 CC = (CC < 32) ? (CC + 32) : CC; 187 break; 188 } 189 O << SPARCCondCodeToString((SPCC::CondCodes)CC); 190 } 191 192 bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum, 193 const MCSubtargetInfo &STI, 194 raw_ostream &O) { 195 llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX."); 196 return true; 197 } 198
