1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "SystemZTargetMachine.h" 11 #include "SystemZTargetTransformInfo.h" 12 #include "llvm/CodeGen/Passes.h" 13 #include "llvm/CodeGen/TargetPassConfig.h" 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Transforms/Scalar.h" 16 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 17 18 using namespace llvm; 19 20 extern cl::opt<bool> MISchedPostRA; 21 extern "C" void LLVMInitializeSystemZTarget() { 22 // Register the target. 23 RegisterTargetMachine<SystemZTargetMachine> X(TheSystemZTarget); 24 } 25 26 // Determine whether we use the vector ABI. 27 static bool UsesVectorABI(StringRef CPU, StringRef FS) { 28 // We use the vector ABI whenever the vector facility is avaiable. 29 // This is the case by default if CPU is z13 or later, and can be 30 // overridden via "[+-]vector" feature string elements. 31 bool VectorABI = true; 32 if (CPU.empty() || CPU == "generic" || 33 CPU == "z10" || CPU == "z196" || CPU == "zEC12") 34 VectorABI = false; 35 36 SmallVector<StringRef, 3> Features; 37 FS.split(Features, ',', -1, false /* KeepEmpty */); 38 for (auto &Feature : Features) { 39 if (Feature == "vector" || Feature == "+vector") 40 VectorABI = true; 41 if (Feature == "-vector") 42 VectorABI = false; 43 } 44 45 return VectorABI; 46 } 47 48 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 49 StringRef FS) { 50 bool VectorABI = UsesVectorABI(CPU, FS); 51 std::string Ret = ""; 52 53 // Big endian. 54 Ret += "E"; 55 56 // Data mangling. 57 Ret += DataLayout::getManglingComponent(TT); 58 59 // Make sure that global data has at least 16 bits of alignment by 60 // default, so that we can refer to it using LARL. We don't have any 61 // special requirements for stack variables though. 62 Ret += "-i1:8:16-i8:8:16"; 63 64 // 64-bit integers are naturally aligned. 65 Ret += "-i64:64"; 66 67 // 128-bit floats are aligned only to 64 bits. 68 Ret += "-f128:64"; 69 70 // When using the vector ABI, 128-bit vectors are also aligned to 64 bits. 71 if (VectorABI) 72 Ret += "-v128:64"; 73 74 // We prefer 16 bits of aligned for all globals; see above. 75 Ret += "-a:8:16"; 76 77 // Integer registers are 32 or 64 bits. 78 Ret += "-n32:64"; 79 80 return Ret; 81 } 82 83 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 84 // Static code is suitable for use in a dynamic executable; there is no 85 // separate DynamicNoPIC model. 86 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC) 87 return Reloc::Static; 88 return *RM; 89 } 90 91 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, 92 StringRef CPU, StringRef FS, 93 const TargetOptions &Options, 94 Optional<Reloc::Model> RM, 95 CodeModel::Model CM, 96 CodeGenOpt::Level OL) 97 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, 98 getEffectiveRelocModel(RM), CM, OL), 99 TLOF(make_unique<TargetLoweringObjectFileELF>()), 100 Subtarget(TT, CPU, FS, *this) { 101 initAsmInfo(); 102 } 103 104 SystemZTargetMachine::~SystemZTargetMachine() {} 105 106 namespace { 107 /// SystemZ Code Generator Pass Configuration Options. 108 class SystemZPassConfig : public TargetPassConfig { 109 public: 110 SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM) 111 : TargetPassConfig(TM, PM) {} 112 113 SystemZTargetMachine &getSystemZTargetMachine() const { 114 return getTM<SystemZTargetMachine>(); 115 } 116 117 void addIRPasses() override; 118 bool addInstSelector() override; 119 void addPreSched2() override; 120 void addPreEmitPass() override; 121 }; 122 } // end anonymous namespace 123 124 void SystemZPassConfig::addIRPasses() { 125 if (getOptLevel() != CodeGenOpt::None) 126 addPass(createSystemZTDCPass()); 127 128 TargetPassConfig::addIRPasses(); 129 } 130 131 bool SystemZPassConfig::addInstSelector() { 132 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel())); 133 134 if (getOptLevel() != CodeGenOpt::None) 135 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine())); 136 137 return false; 138 } 139 140 void SystemZPassConfig::addPreSched2() { 141 if (getOptLevel() != CodeGenOpt::None) 142 addPass(&IfConverterID); 143 } 144 145 void SystemZPassConfig::addPreEmitPass() { 146 147 // Do instruction shortening before compare elimination because some 148 // vector instructions will be shortened into opcodes that compare 149 // elimination recognizes. 150 if (getOptLevel() != CodeGenOpt::None) 151 addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false); 152 153 // We eliminate comparisons here rather than earlier because some 154 // transformations can change the set of available CC values and we 155 // generally want those transformations to have priority. This is 156 // especially true in the commonest case where the result of the comparison 157 // is used by a single in-range branch instruction, since we will then 158 // be able to fuse the compare and the branch instead. 159 // 160 // For example, two-address NILF can sometimes be converted into 161 // three-address RISBLG. NILF produces a CC value that indicates whether 162 // the low word is zero, but RISBLG does not modify CC at all. On the 163 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG. 164 // The CC value produced by NILL isn't useful for our purposes, but the 165 // value produced by RISBG can be used for any comparison with zero 166 // (not just equality). So there are some transformations that lose 167 // CC values (while still being worthwhile) and others that happen to make 168 // the CC result more useful than it was originally. 169 // 170 // Another reason is that we only want to use BRANCH ON COUNT in cases 171 // where we know that the count register is not going to be spilled. 172 // 173 // Doing it so late makes it more likely that a register will be reused 174 // between the comparison and the branch, but it isn't clear whether 175 // preventing that would be a win or not. 176 if (getOptLevel() != CodeGenOpt::None) 177 addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false); 178 addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); 179 180 // Do final scheduling after all other optimizations, to get an 181 // optimal input for the decoder (branch relaxation must happen 182 // after block placement). 183 if (getOptLevel() != CodeGenOpt::None) { 184 if (MISchedPostRA) 185 addPass(&PostMachineSchedulerID); 186 else 187 addPass(&PostRASchedulerID); 188 } 189 } 190 191 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { 192 return new SystemZPassConfig(this, PM); 193 } 194 195 TargetIRAnalysis SystemZTargetMachine::getTargetIRAnalysis() { 196 return TargetIRAnalysis([this](const Function &F) { 197 return TargetTransformInfo(SystemZTTIImpl(this, F)); 198 }); 199 } 200
