1 //==- WebAssemblyDisassembler.cpp - Disassembler for WebAssembly -*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file is part of the WebAssembly Disassembler. 12 /// 13 /// It contains code to translate the data produced by the decoder into 14 /// MCInsts. 15 /// 16 //===----------------------------------------------------------------------===// 17 18 #include "WebAssembly.h" 19 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/MCSymbol.h" 26 #include "llvm/Support/Endian.h" 27 #include "llvm/Support/TargetRegistry.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm-disassembler" 31 32 namespace { 33 class WebAssemblyDisassembler final : public MCDisassembler { 34 std::unique_ptr<const MCInstrInfo> MCII; 35 36 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 37 ArrayRef<uint8_t> Bytes, uint64_t Address, 38 raw_ostream &VStream, 39 raw_ostream &CStream) const override; 40 41 public: 42 WebAssemblyDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 43 std::unique_ptr<const MCInstrInfo> MCII) 44 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {} 45 }; 46 } // end anonymous namespace 47 48 static MCDisassembler *createWebAssemblyDisassembler(const Target &T, 49 const MCSubtargetInfo &STI, 50 MCContext &Ctx) { 51 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo()); 52 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII)); 53 } 54 55 extern "C" void LLVMInitializeWebAssemblyDisassembler() { 56 // Register the disassembler for each target. 57 TargetRegistry::RegisterMCDisassembler(TheWebAssemblyTarget32, 58 createWebAssemblyDisassembler); 59 TargetRegistry::RegisterMCDisassembler(TheWebAssemblyTarget64, 60 createWebAssemblyDisassembler); 61 } 62 63 MCDisassembler::DecodeStatus WebAssemblyDisassembler::getInstruction( 64 MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/, 65 raw_ostream &OS, raw_ostream &CS) const { 66 Size = 0; 67 uint64_t Pos = 0; 68 69 // Read the opcode. 70 if (Pos + sizeof(uint64_t) > Bytes.size()) 71 return MCDisassembler::Fail; 72 uint64_t Opcode = support::endian::read64le(Bytes.data() + Pos); 73 Pos += sizeof(uint64_t); 74 75 if (Opcode >= WebAssembly::INSTRUCTION_LIST_END) 76 return MCDisassembler::Fail; 77 78 MI.setOpcode(Opcode); 79 const MCInstrDesc &Desc = MCII->get(Opcode); 80 unsigned NumFixedOperands = Desc.NumOperands; 81 82 // If it's variadic, read the number of extra operands. 83 unsigned NumExtraOperands = 0; 84 if (Desc.isVariadic()) { 85 if (Pos + sizeof(uint64_t) > Bytes.size()) 86 return MCDisassembler::Fail; 87 NumExtraOperands = support::endian::read64le(Bytes.data() + Pos); 88 Pos += sizeof(uint64_t); 89 } 90 91 // Read the fixed operands. These are described by the MCInstrDesc. 92 for (unsigned i = 0; i < NumFixedOperands; ++i) { 93 const MCOperandInfo &Info = Desc.OpInfo[i]; 94 switch (Info.OperandType) { 95 case MCOI::OPERAND_IMMEDIATE: 96 case WebAssembly::OPERAND_P2ALIGN: 97 case WebAssembly::OPERAND_BASIC_BLOCK: { 98 if (Pos + sizeof(uint64_t) > Bytes.size()) 99 return MCDisassembler::Fail; 100 uint64_t Imm = support::endian::read64le(Bytes.data() + Pos); 101 Pos += sizeof(uint64_t); 102 MI.addOperand(MCOperand::createImm(Imm)); 103 break; 104 } 105 case MCOI::OPERAND_REGISTER: { 106 if (Pos + sizeof(uint64_t) > Bytes.size()) 107 return MCDisassembler::Fail; 108 uint64_t Reg = support::endian::read64le(Bytes.data() + Pos); 109 Pos += sizeof(uint64_t); 110 MI.addOperand(MCOperand::createReg(Reg)); 111 break; 112 } 113 case WebAssembly::OPERAND_FP32IMM: 114 case WebAssembly::OPERAND_FP64IMM: { 115 // TODO: MC converts all floating point immediate operands to double. 116 // This is fine for numeric values, but may cause NaNs to change bits. 117 if (Pos + sizeof(uint64_t) > Bytes.size()) 118 return MCDisassembler::Fail; 119 uint64_t Bits = support::endian::read64le(Bytes.data() + Pos); 120 Pos += sizeof(uint64_t); 121 double Imm; 122 memcpy(&Imm, &Bits, sizeof(Imm)); 123 MI.addOperand(MCOperand::createFPImm(Imm)); 124 break; 125 } 126 default: 127 llvm_unreachable("unimplemented operand kind"); 128 } 129 } 130 131 // Read the extra operands. 132 assert(NumExtraOperands == 0 || Desc.isVariadic()); 133 for (unsigned i = 0; i < NumExtraOperands; ++i) { 134 if (Pos + sizeof(uint64_t) > Bytes.size()) 135 return MCDisassembler::Fail; 136 if (Desc.TSFlags & WebAssemblyII::VariableOpIsImmediate) { 137 // Decode extra immediate operands. 138 uint64_t Imm = support::endian::read64le(Bytes.data() + Pos); 139 MI.addOperand(MCOperand::createImm(Imm)); 140 } else { 141 // Decode extra register operands. 142 uint64_t Reg = support::endian::read64le(Bytes.data() + Pos); 143 MI.addOperand(MCOperand::createReg(Reg)); 144 } 145 Pos += sizeof(uint64_t); 146 } 147 148 Size = Pos; 149 return MCDisassembler::Success; 150 } 151
