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      1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file describes the X86 instructions that are generally used in
     11 // privileged modes.  These are not typically used by the compiler, but are
     12 // supported for the assembler and disassembler.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 let SchedRW = [WriteSystem] in {
     17 let Defs = [RAX, RDX] in
     18   def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
     19               TB;
     20 
     21 let Defs = [RAX, RCX, RDX] in
     22   def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
     23 
     24 // CPU flow control instructions
     25 
     26 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
     27   def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
     28   def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
     29 }
     30 
     31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
     32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
     33 
     34 // Interrupt and SysCall Instructions.
     35 let Uses = [EFLAGS] in
     36   def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
     37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
     38               [(int_x86_int (i8 3))], IIC_INT3>;
     39 } // SchedRW
     40 
     41 // The long form of "int $3" turns into int3 as a size optimization.
     42 // FIXME: This doesn't work because InstAlias can't match immediate constants.
     43 //def : InstAlias<"int\t$3", (INT3)>;
     44 
     45 let SchedRW = [WriteSystem] in {
     46 
     47 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
     48               [(int_x86_int imm:$trap)], IIC_INT>;
     49 
     50 
     51 def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
     52 def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
     53 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
     54                Requires<[In64BitMode]>;
     55 
     56 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
     57                  IIC_SYS_ENTER_EXIT>, TB;
     58 
     59 def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
     60                  IIC_SYS_ENTER_EXIT>, TB;
     61 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
     62                  IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
     63 } // SchedRW
     64 
     65 def : Pat<(debugtrap),
     66           (INT3)>, Requires<[NotPS4]>;
     67 def : Pat<(debugtrap),
     68           (INT (i8 0x41))>, Requires<[IsPS4]>;
     69 
     70 //===----------------------------------------------------------------------===//
     71 //  Input/Output Instructions.
     72 //
     73 let SchedRW = [WriteSystem] in {
     74 let Defs = [AL], Uses = [DX] in
     75 def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
     76                "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
     77 let Defs = [AX], Uses = [DX] in
     78 def IN16rr : I<0xED, RawFrm, (outs), (ins),
     79                "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
     80 let Defs = [EAX], Uses = [DX] in
     81 def IN32rr : I<0xED, RawFrm, (outs), (ins),
     82                "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
     83 
     84 let Defs = [AL] in
     85 def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
     86                   "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
     87 let Defs = [AX] in
     88 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
     89                   "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
     90 let Defs = [EAX] in
     91 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
     92                   "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
     93 
     94 let Uses = [DX, AL] in
     95 def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
     96                 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
     97 let Uses = [DX, AX] in
     98 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
     99                 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
    100 let Uses = [DX, EAX] in
    101 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
    102                 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
    103 
    104 let Uses = [AL] in
    105 def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
    106                    "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
    107 let Uses = [AX] in
    108 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
    109                    "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
    110 let Uses = [EAX] in
    111 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
    112                   "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
    113 
    114 } // SchedRW
    115 
    116 //===----------------------------------------------------------------------===//
    117 // Moves to and from debug registers
    118 
    119 let SchedRW = [WriteSystem] in {
    120 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
    121                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
    122                 Requires<[Not64BitMode]>;
    123 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
    124                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
    125                 Requires<[In64BitMode]>;
    126 
    127 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
    128                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
    129                 Requires<[Not64BitMode]>;
    130 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
    131                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
    132                 Requires<[In64BitMode]>;
    133 } // SchedRW
    134 
    135 //===----------------------------------------------------------------------===//
    136 // Moves to and from control registers
    137 
    138 let SchedRW = [WriteSystem] in {
    139 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
    140                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
    141                 Requires<[Not64BitMode]>;
    142 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
    143                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
    144                 Requires<[In64BitMode]>;
    145 
    146 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
    147                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
    148                 Requires<[Not64BitMode]>;
    149 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
    150                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
    151                 Requires<[In64BitMode]>;
    152 } // SchedRW
    153 
    154 //===----------------------------------------------------------------------===//
    155 // Segment override instruction prefixes
    156 
    157 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
    158 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
    159 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
    160 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
    161 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
    162 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
    163 
    164 
    165 //===----------------------------------------------------------------------===//
    166 // Moves to and from segment registers.
    167 //
    168 
    169 let SchedRW = [WriteMove] in {
    170 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
    171                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
    172 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
    173                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
    174 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
    175                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
    176 
    177 def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
    178                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
    179 def MOV32ms : I<0x8C, MRMDestMem, (outs), (ins i32mem:$dst, SEGMENT_REG:$src),
    180                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
    181 def MOV64ms : RI<0x8C, MRMDestMem, (outs), (ins i64mem:$dst, SEGMENT_REG:$src),
    182                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
    183 
    184 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
    185                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
    186 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
    187                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
    188 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
    189                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
    190 
    191 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
    192                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
    193 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
    194                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
    195 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
    196                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
    197 } // SchedRW
    198 
    199 //===----------------------------------------------------------------------===//
    200 // Segmentation support instructions.
    201 
    202 let SchedRW = [WriteSystem] in {
    203 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
    204 
    205 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
    206                 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
    207                 OpSize16;
    208 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
    209                 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
    210                 OpSize16;
    211 
    212 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
    213 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
    214                 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
    215                 OpSize32;
    216 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
    217                 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
    218                 OpSize32;
    219 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
    220 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
    221                  "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
    222 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
    223                  "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
    224 
    225 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
    226                 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
    227                 OpSize16;
    228 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
    229                 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
    230                 OpSize16;
    231 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
    232                 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
    233                 OpSize32;
    234 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
    235                 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
    236                 OpSize32;
    237 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
    238                  "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
    239 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
    240                  "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
    241 
    242 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
    243                [], IIC_INVLPG>, TB;
    244 
    245 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
    246                "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
    247 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
    248                "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
    249 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
    250                 "str{q}\t$dst", [], IIC_STR>, TB;
    251 def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
    252                "str{w}\t$dst", [], IIC_STR>, TB;
    253 
    254 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
    255              "ltr{w}\t$src", [], IIC_LTR>, TB;
    256 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
    257              "ltr{w}\t$src", [], IIC_LTR>, TB;
    258 
    259 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
    260                  "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
    261                  OpSize16, Requires<[Not64BitMode]>;
    262 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
    263                  "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
    264                  OpSize32, Requires<[Not64BitMode]>;
    265 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
    266                  "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
    267                  OpSize16, Requires<[Not64BitMode]>;
    268 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
    269                  "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
    270                  OpSize32, Requires<[Not64BitMode]>;
    271 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
    272                  "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
    273                  OpSize16, Requires<[Not64BitMode]>;
    274 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
    275                  "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
    276                  OpSize32, Requires<[Not64BitMode]>;
    277 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
    278                  "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
    279                  OpSize16, Requires<[Not64BitMode]>;
    280 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
    281                  "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
    282                  OpSize32, Requires<[Not64BitMode]>;
    283 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
    284                  "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
    285 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
    286                  "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
    287                OpSize32, Requires<[Not64BitMode]>;
    288 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
    289                  "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
    290 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
    291                  "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
    292                OpSize32, Requires<[Not64BitMode]>;
    293 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
    294                  "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
    295                OpSize32, Requires<[In64BitMode]>;
    296 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
    297                  "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
    298                OpSize32, Requires<[In64BitMode]>;
    299 
    300 // No "pop cs" instruction.
    301 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
    302                 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
    303               OpSize16, Requires<[Not64BitMode]>;
    304 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
    305                 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
    306               OpSize32, Requires<[Not64BitMode]>;
    307 
    308 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
    309                 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
    310               OpSize16, Requires<[Not64BitMode]>;
    311 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
    312                 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
    313               OpSize32, Requires<[Not64BitMode]>;
    314 
    315 def POPES16 : I<0x07, RawFrm, (outs), (ins),
    316                 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
    317               OpSize16, Requires<[Not64BitMode]>;
    318 def POPES32 : I<0x07, RawFrm, (outs), (ins),
    319                 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
    320               OpSize32, Requires<[Not64BitMode]>;
    321 
    322 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
    323                 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
    324 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
    325                 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
    326               OpSize32, Requires<[Not64BitMode]>;
    327 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
    328                 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
    329               OpSize32, Requires<[In64BitMode]>;
    330 
    331 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
    332                 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
    333 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
    334                 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
    335               OpSize32, Requires<[Not64BitMode]>;
    336 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
    337                 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
    338               OpSize32, Requires<[In64BitMode]>;
    339 
    340 
    341 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    342                 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
    343                 Requires<[Not64BitMode]>;
    344 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    345                 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
    346                 Requires<[Not64BitMode]>;
    347 
    348 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    349                 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
    350 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    351                 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
    352 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
    353                  "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
    354 
    355 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    356                 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
    357                 Requires<[Not64BitMode]>;
    358 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    359                 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
    360                 Requires<[Not64BitMode]>;
    361 
    362 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    363                 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
    364 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    365                 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
    366 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
    367                  "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
    368 
    369 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    370                 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
    371 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    372                 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
    373 
    374 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
    375                  "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
    376 
    377 
    378 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
    379               "verr\t$seg", [], IIC_VERR>, TB;
    380 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
    381               "verr\t$seg", [], IIC_VERR>, TB;
    382 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
    383               "verw\t$seg", [], IIC_VERW_MEM>, TB;
    384 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
    385               "verw\t$seg", [], IIC_VERW_REG>, TB;
    386 } // SchedRW
    387 
    388 //===----------------------------------------------------------------------===//
    389 // Descriptor-table support instructions
    390 
    391 let SchedRW = [WriteSystem] in {
    392 def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
    393               "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    394 def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
    395               "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
    396 def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
    397               "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
    398 def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
    399               "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    400 def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
    401               "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
    402 def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
    403               "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
    404 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
    405                 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
    406 def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
    407                 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
    408 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
    409                 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
    410 
    411 // LLDT is not interpreted specially in 64-bit mode because there is no sign
    412 //   extension.
    413 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
    414                  "sldt{q}\t$dst", [], IIC_SLDT>, TB;
    415 def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
    416                  "sldt{q}\t$dst", [], IIC_SLDT>, TB;
    417 
    418 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
    419               "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    420 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
    421               "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
    422 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
    423               "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
    424 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
    425               "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    426 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
    427               "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
    428 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
    429               "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
    430 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
    431                 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
    432 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
    433                 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
    434 } // SchedRW
    435 
    436 //===----------------------------------------------------------------------===//
    437 // Specialized register support
    438 let SchedRW = [WriteSystem] in {
    439 let Uses = [EAX, ECX, EDX] in
    440 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
    441 let Defs = [EAX, EDX], Uses = [ECX] in
    442 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
    443 
    444 let Defs = [RAX, RDX], Uses = [ECX] in
    445   def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
    446               TB;
    447 
    448 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
    449                 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
    450 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
    451                 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
    452 // no m form encodable; use SMSW16m
    453 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
    454                  "smsw{q}\t$dst", [], IIC_SMSW>, TB;
    455 
    456 // For memory operands, there is only a 16-bit form
    457 def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
    458                 "smsw{w}\t$dst", [], IIC_SMSW>, TB;
    459 
    460 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
    461                 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
    462 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
    463                 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
    464 
    465 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
    466   def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
    467 } // SchedRW
    468 
    469 //===----------------------------------------------------------------------===//
    470 // Cache instructions
    471 let SchedRW = [WriteSystem] in {
    472 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
    473 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
    474 } // SchedRW
    475 
    476 //===----------------------------------------------------------------------===//
    477 // XSAVE instructions
    478 let SchedRW = [WriteSystem] in {
    479 let Predicates = [HasXSAVE] in {
    480 let Defs = [EDX, EAX], Uses = [ECX] in
    481   def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
    482 
    483 let Uses = [EDX, EAX, ECX] in
    484   def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
    485 }
    486 
    487 let Uses = [EDX, EAX] in {
    488 let Predicates = [HasXSAVE] in {
    489   def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
    490                 "xsave\t$dst",
    491                 [(int_x86_xsave addr:$dst, EDX, EAX)]>, TB;
    492   def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
    493                    "xsave64\t$dst",
    494                    [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
    495   def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
    496                  "xrstor\t$dst",
    497                  [(int_x86_xrstor addr:$dst, EDX, EAX)]>, TB;
    498   def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
    499                     "xrstor64\t$dst",
    500                     [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
    501 }
    502 let Predicates = [HasXSAVEOPT] in {
    503   def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
    504                    "xsaveopt\t$dst",
    505                    [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS;
    506   def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
    507                       "xsaveopt64\t$dst",
    508                       [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
    509 }
    510 let Predicates = [HasXSAVEC] in {
    511   def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
    512                  "xsavec\t$dst",
    513                  [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB;
    514   def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
    515                    "xsavec64\t$dst",
    516                    [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
    517 }
    518 let Predicates = [HasXSAVES] in {
    519   def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
    520                  "xsaves\t$dst",
    521                  [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB;
    522   def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
    523                     "xsaves64\t$dst",
    524                     [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
    525   def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
    526                   "xrstors\t$dst",
    527                   [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB;
    528   def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
    529                      "xrstors64\t$dst",
    530                      [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
    531 }
    532 } // Uses
    533 } // SchedRW
    534 
    535 //===----------------------------------------------------------------------===//
    536 // VIA PadLock crypto instructions
    537 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
    538   def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
    539 
    540 def : InstAlias<"xstorerng", (XSTORE)>;
    541 
    542 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
    543   def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
    544   def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
    545   def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
    546   def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
    547   def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
    548 }
    549 
    550 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
    551   def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
    552   def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
    553 }
    554 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
    555   def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
    556 //==-----------------------------------------------------------------------===//
    557 // PKU  - enable protection key
    558 let usesCustomInserter = 1 in {
    559   def WRPKRU : PseudoI<(outs), (ins GR32:$src),
    560                 [(int_x86_wrpkru GR32:$src)]>;
    561   def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
    562                 [(set GR32:$dst, (int_x86_rdpkru))]>;
    563 }
    564 
    565 let Defs = [EAX, EDX], Uses = [ECX] in
    566   def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB;
    567 let Uses = [EAX, ECX, EDX] in
    568   def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB;
    569 
    570 //===----------------------------------------------------------------------===//
    571 // FS/GS Base Instructions
    572 let Predicates = [HasFSGSBase, In64BitMode] in {
    573   def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
    574                    "rdfsbase{l}\t$dst",
    575                    [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
    576   def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
    577                      "rdfsbase{q}\t$dst",
    578                      [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
    579   def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
    580                    "rdgsbase{l}\t$dst",
    581                    [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
    582   def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
    583                      "rdgsbase{q}\t$dst",
    584                      [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
    585   def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
    586                    "wrfsbase{l}\t$src",
    587                    [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
    588   def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
    589                       "wrfsbase{q}\t$src",
    590                       [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
    591   def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
    592                    "wrgsbase{l}\t$src",
    593                    [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
    594   def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
    595                       "wrgsbase{q}\t$src",
    596                       [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
    597 }
    598 
    599 //===----------------------------------------------------------------------===//
    600 // INVPCID Instruction
    601 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
    602                 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
    603                 Requires<[Not64BitMode]>;
    604 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
    605                 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
    606                 Requires<[In64BitMode]>;
    607 
    608 //===----------------------------------------------------------------------===//
    609 // SMAP Instruction
    610 let Defs = [EFLAGS] in {
    611   def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
    612   def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
    613 }
    614 
    615 //===----------------------------------------------------------------------===//
    616 // SMX Instruction
    617 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
    618   def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
    619 }
    620