1 //===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the instructions that make up the Intel TSX instruction 11 // set. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // TSX instructions 17 18 def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, 19 [SDNPHasChain, SDNPSideEffect]>; 20 21 let usesCustomInserter = 1 in 22 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins), 23 "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>, 24 Requires<[HasRTM]>; 25 26 let isBranch = 1, isTerminator = 1, Defs = [EAX] in { 27 def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst), 28 "xbegin\t$dst", []>, OpSize16, Requires<[HasRTM]>; 29 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), 30 "xbegin\t$dst", []>, OpSize32, Requires<[HasRTM]>; 31 } 32 33 def XEND : I<0x01, MRM_D5, (outs), (ins), 34 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>; 35 36 let Defs = [EFLAGS] in 37 def XTEST : I<0x01, MRM_D6, (outs), (ins), 38 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>; 39 40 def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm), 41 "xabort\t$imm", 42 [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>; 43 44 // HLE prefixes 45 46 let isAsmParserOnly = 1 in { 47 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>, Requires<[HasHLE]>; 48 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>, Requires<[HasHLE]>; 49 } 50 51
