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      1 //===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 // InstrSchedModel annotations for out-of-order CPUs.
     11 //
     12 // These annotations are independent of the itinerary classes defined below.
     13 
     14 // Instructions with folded loads need to read the memory operand immediately,
     15 // but other register operands don't have to be read until the load is ready.
     16 // These operands are marked with ReadAfterLd.
     17 def ReadAfterLd : SchedRead;
     18 
     19 // Instructions with both a load and a store folded are modeled as a folded
     20 // load + WriteRMW.
     21 def WriteRMW : SchedWrite;
     22 
     23 // Most instructions can fold loads, so almost every SchedWrite comes in two
     24 // variants: With and without a folded load.
     25 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
     26 // with a folded load.
     27 class X86FoldableSchedWrite : SchedWrite {
     28   // The SchedWrite to use when a load is folded into the instruction.
     29   SchedWrite Folded;
     30 }
     31 
     32 // Multiclass that produces a linked pair of SchedWrites.
     33 multiclass X86SchedWritePair {
     34   // Register-Memory operation.
     35   def Ld : SchedWrite;
     36   // Register-Register operation.
     37   def NAME : X86FoldableSchedWrite {
     38     let Folded = !cast<SchedWrite>(NAME#"Ld");
     39   }
     40 }
     41 
     42 // Arithmetic.
     43 defm WriteALU  : X86SchedWritePair; // Simple integer ALU op.
     44 defm WriteIMul : X86SchedWritePair; // Integer multiplication.
     45 def  WriteIMulH : SchedWrite;       // Integer multiplication, high part.
     46 defm WriteIDiv : X86SchedWritePair; // Integer division.
     47 def  WriteLEA  : SchedWrite;        // LEA instructions can't fold loads.
     48 
     49 // Integer shifts and rotates.
     50 defm WriteShift : X86SchedWritePair;
     51 
     52 // Loads, stores, and moves, not folded with other operations.
     53 def WriteLoad  : SchedWrite;
     54 def WriteStore : SchedWrite;
     55 def WriteMove  : SchedWrite;
     56 
     57 // Idioms that clear a register, like xorps %xmm0, %xmm0.
     58 // These can often bypass execution ports completely.
     59 def WriteZero : SchedWrite;
     60 
     61 // Branches don't produce values, so they have no latency, but they still
     62 // consume resources. Indirect branches can fold loads.
     63 defm WriteJump : X86SchedWritePair;
     64 
     65 // Floating point. This covers both scalar and vector operations.
     66 defm WriteFAdd   : X86SchedWritePair; // Floating point add/sub/compare.
     67 defm WriteFMul   : X86SchedWritePair; // Floating point multiplication.
     68 defm WriteFDiv   : X86SchedWritePair; // Floating point division.
     69 defm WriteFSqrt  : X86SchedWritePair; // Floating point square root.
     70 defm WriteFRcp   : X86SchedWritePair; // Floating point reciprocal estimate.
     71 defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate.
     72 defm WriteFMA    : X86SchedWritePair; // Fused Multiply Add.
     73 defm WriteFShuffle  : X86SchedWritePair; // Floating point vector shuffles.
     74 defm WriteFBlend  : X86SchedWritePair; // Floating point vector blends.
     75 defm WriteFVarBlend  : X86SchedWritePair; // Fp vector variable blends.
     76 
     77 // FMA Scheduling helper class.
     78 class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
     79 
     80 // Vector integer operations.
     81 defm WriteVecALU   : X86SchedWritePair; // Vector integer ALU op, no logicals.
     82 defm WriteVecShift : X86SchedWritePair; // Vector integer shifts.
     83 defm WriteVecIMul  : X86SchedWritePair; // Vector integer multiply.
     84 defm WriteShuffle  : X86SchedWritePair; // Vector shuffles.
     85 defm WriteBlend  : X86SchedWritePair; // Vector blends.
     86 defm WriteVarBlend  : X86SchedWritePair; // Vector variable blends.
     87 defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
     88 
     89 // Vector bitwise operations.
     90 // These are often used on both floating point and integer vectors.
     91 defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
     92 
     93 // Conversion between integer and float.
     94 defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
     95 defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
     96 defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
     97 
     98 // Strings instructions.
     99 // Packed Compare Implicit Length Strings, Return Mask
    100 defm WritePCmpIStrM : X86SchedWritePair;
    101 // Packed Compare Explicit Length Strings, Return Mask
    102 defm WritePCmpEStrM : X86SchedWritePair;
    103 // Packed Compare Implicit Length Strings, Return Index
    104 defm WritePCmpIStrI : X86SchedWritePair;
    105 // Packed Compare Explicit Length Strings, Return Index
    106 defm WritePCmpEStrI : X86SchedWritePair;
    107 
    108 // AES instructions.
    109 defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption.
    110 defm WriteAESIMC : X86SchedWritePair; // InvMixColumn.
    111 defm WriteAESKeyGen : X86SchedWritePair; // Key Generation.
    112 
    113 // Carry-less multiplication instructions.
    114 defm WriteCLMul : X86SchedWritePair;
    115 
    116 // Catch-all for expensive system instructions.
    117 def WriteSystem : SchedWrite;
    118 
    119 // AVX2.
    120 defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
    121 defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
    122 defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts.
    123 
    124 // Old microcoded instructions that nobody use.
    125 def WriteMicrocoded : SchedWrite;
    126 
    127 // Fence instructions.
    128 def WriteFence : SchedWrite;
    129 
    130 // Nop, not very useful expect it provides a model for nops!
    131 def WriteNop : SchedWrite;
    132 
    133 //===----------------------------------------------------------------------===//
    134 // Instruction Itinerary classes used for X86
    135 def IIC_ALU_MEM     : InstrItinClass;
    136 def IIC_ALU_NONMEM  : InstrItinClass;
    137 def IIC_LEA         : InstrItinClass;
    138 def IIC_LEA_16      : InstrItinClass;
    139 def IIC_MUL8        : InstrItinClass;
    140 def IIC_MUL16_MEM   : InstrItinClass;
    141 def IIC_MUL16_REG   : InstrItinClass;
    142 def IIC_MUL32_MEM   : InstrItinClass;
    143 def IIC_MUL32_REG   : InstrItinClass;
    144 def IIC_MUL64       : InstrItinClass;
    145 // imul by al, ax, eax, tax
    146 def IIC_IMUL8       : InstrItinClass;
    147 def IIC_IMUL16_MEM  : InstrItinClass;
    148 def IIC_IMUL16_REG  : InstrItinClass;
    149 def IIC_IMUL32_MEM  : InstrItinClass;
    150 def IIC_IMUL32_REG  : InstrItinClass;
    151 def IIC_IMUL64      : InstrItinClass;
    152 // imul reg by reg|mem
    153 def IIC_IMUL16_RM   : InstrItinClass;
    154 def IIC_IMUL16_RR   : InstrItinClass;
    155 def IIC_IMUL32_RM   : InstrItinClass;
    156 def IIC_IMUL32_RR   : InstrItinClass;
    157 def IIC_IMUL64_RM   : InstrItinClass;
    158 def IIC_IMUL64_RR   : InstrItinClass;
    159 // imul reg = reg/mem * imm
    160 def IIC_IMUL16_RMI  : InstrItinClass;
    161 def IIC_IMUL16_RRI  : InstrItinClass;
    162 def IIC_IMUL32_RMI  : InstrItinClass;
    163 def IIC_IMUL32_RRI  : InstrItinClass;
    164 def IIC_IMUL64_RMI  : InstrItinClass;
    165 def IIC_IMUL64_RRI  : InstrItinClass;
    166 // div
    167 def IIC_DIV8_MEM    : InstrItinClass;
    168 def IIC_DIV8_REG    : InstrItinClass;
    169 def IIC_DIV16       : InstrItinClass;
    170 def IIC_DIV32       : InstrItinClass;
    171 def IIC_DIV64       : InstrItinClass;
    172 // idiv
    173 def IIC_IDIV8       : InstrItinClass;
    174 def IIC_IDIV16      : InstrItinClass;
    175 def IIC_IDIV32      : InstrItinClass;
    176 def IIC_IDIV64      : InstrItinClass;
    177 // neg/not/inc/dec
    178 def IIC_UNARY_REG   : InstrItinClass;
    179 def IIC_UNARY_MEM   : InstrItinClass;
    180 // add/sub/and/or/xor/sbc/cmp/test
    181 def IIC_BIN_MEM     : InstrItinClass;
    182 def IIC_BIN_NONMEM  : InstrItinClass;
    183 // adc/sbc
    184 def IIC_BIN_CARRY_MEM     : InstrItinClass;
    185 def IIC_BIN_CARRY_NONMEM  : InstrItinClass;
    186 // shift/rotate
    187 def IIC_SR          : InstrItinClass;
    188 // shift double
    189 def IIC_SHD16_REG_IM : InstrItinClass;
    190 def IIC_SHD16_REG_CL : InstrItinClass;
    191 def IIC_SHD16_MEM_IM : InstrItinClass;
    192 def IIC_SHD16_MEM_CL : InstrItinClass;
    193 def IIC_SHD32_REG_IM : InstrItinClass;
    194 def IIC_SHD32_REG_CL : InstrItinClass;
    195 def IIC_SHD32_MEM_IM : InstrItinClass;
    196 def IIC_SHD32_MEM_CL : InstrItinClass;
    197 def IIC_SHD64_REG_IM : InstrItinClass;
    198 def IIC_SHD64_REG_CL : InstrItinClass;
    199 def IIC_SHD64_MEM_IM : InstrItinClass;
    200 def IIC_SHD64_MEM_CL : InstrItinClass;
    201 // cmov
    202 def IIC_CMOV16_RM : InstrItinClass;
    203 def IIC_CMOV16_RR : InstrItinClass;
    204 def IIC_CMOV32_RM : InstrItinClass;
    205 def IIC_CMOV32_RR : InstrItinClass;
    206 def IIC_CMOV64_RM : InstrItinClass;
    207 def IIC_CMOV64_RR : InstrItinClass;
    208 // set
    209 def IIC_SET_R : InstrItinClass;
    210 def IIC_SET_M : InstrItinClass;
    211 // jmp/jcc/jcxz
    212 def IIC_Jcc : InstrItinClass;
    213 def IIC_JCXZ : InstrItinClass;
    214 def IIC_JMP_REL : InstrItinClass;
    215 def IIC_JMP_REG : InstrItinClass;
    216 def IIC_JMP_MEM : InstrItinClass;
    217 def IIC_JMP_FAR_MEM : InstrItinClass;
    218 def IIC_JMP_FAR_PTR : InstrItinClass;
    219 // loop
    220 def IIC_LOOP : InstrItinClass;
    221 def IIC_LOOPE : InstrItinClass;
    222 def IIC_LOOPNE : InstrItinClass;
    223 // call
    224 def IIC_CALL_RI : InstrItinClass;
    225 def IIC_CALL_MEM : InstrItinClass;
    226 def IIC_CALL_FAR_MEM : InstrItinClass;
    227 def IIC_CALL_FAR_PTR : InstrItinClass;
    228 // ret
    229 def IIC_RET : InstrItinClass;
    230 def IIC_RET_IMM : InstrItinClass;
    231 //sign extension movs
    232 def IIC_MOVSX : InstrItinClass;
    233 def IIC_MOVSX_R16_R8 : InstrItinClass;
    234 def IIC_MOVSX_R16_M8 : InstrItinClass;
    235 def IIC_MOVSX_R16_R16 : InstrItinClass;
    236 def IIC_MOVSX_R32_R32 : InstrItinClass;
    237 //zero extension movs
    238 def IIC_MOVZX : InstrItinClass;
    239 def IIC_MOVZX_R16_R8 : InstrItinClass;
    240 def IIC_MOVZX_R16_M8 : InstrItinClass;
    241 
    242 def IIC_REP_MOVS : InstrItinClass;
    243 def IIC_REP_STOS : InstrItinClass;
    244 
    245 // SSE scalar/parallel binary operations
    246 def IIC_SSE_ALU_F32S_RR : InstrItinClass;
    247 def IIC_SSE_ALU_F32S_RM : InstrItinClass;
    248 def IIC_SSE_ALU_F64S_RR : InstrItinClass;
    249 def IIC_SSE_ALU_F64S_RM : InstrItinClass;
    250 def IIC_SSE_MUL_F32S_RR : InstrItinClass;
    251 def IIC_SSE_MUL_F32S_RM : InstrItinClass;
    252 def IIC_SSE_MUL_F64S_RR : InstrItinClass;
    253 def IIC_SSE_MUL_F64S_RM : InstrItinClass;
    254 def IIC_SSE_DIV_F32S_RR : InstrItinClass;
    255 def IIC_SSE_DIV_F32S_RM : InstrItinClass;
    256 def IIC_SSE_DIV_F64S_RR : InstrItinClass;
    257 def IIC_SSE_DIV_F64S_RM : InstrItinClass;
    258 def IIC_SSE_ALU_F32P_RR : InstrItinClass;
    259 def IIC_SSE_ALU_F32P_RM : InstrItinClass;
    260 def IIC_SSE_ALU_F64P_RR : InstrItinClass;
    261 def IIC_SSE_ALU_F64P_RM : InstrItinClass;
    262 def IIC_SSE_MUL_F32P_RR : InstrItinClass;
    263 def IIC_SSE_MUL_F32P_RM : InstrItinClass;
    264 def IIC_SSE_MUL_F64P_RR : InstrItinClass;
    265 def IIC_SSE_MUL_F64P_RM : InstrItinClass;
    266 def IIC_SSE_DIV_F32P_RR : InstrItinClass;
    267 def IIC_SSE_DIV_F32P_RM : InstrItinClass;
    268 def IIC_SSE_DIV_F64P_RR : InstrItinClass;
    269 def IIC_SSE_DIV_F64P_RM : InstrItinClass;
    270 
    271 def IIC_SSE_COMIS_RR : InstrItinClass;
    272 def IIC_SSE_COMIS_RM : InstrItinClass;
    273 
    274 def IIC_SSE_HADDSUB_RR : InstrItinClass;
    275 def IIC_SSE_HADDSUB_RM : InstrItinClass;
    276 
    277 def IIC_SSE_BIT_P_RR  : InstrItinClass;
    278 def IIC_SSE_BIT_P_RM  : InstrItinClass;
    279 
    280 def IIC_SSE_INTALU_P_RR  : InstrItinClass;
    281 def IIC_SSE_INTALU_P_RM  : InstrItinClass;
    282 def IIC_SSE_INTALUQ_P_RR  : InstrItinClass;
    283 def IIC_SSE_INTALUQ_P_RM  : InstrItinClass;
    284 
    285 def IIC_SSE_INTMUL_P_RR : InstrItinClass;
    286 def IIC_SSE_INTMUL_P_RM : InstrItinClass;
    287 
    288 def IIC_SSE_INTSH_P_RR : InstrItinClass;
    289 def IIC_SSE_INTSH_P_RM : InstrItinClass;
    290 def IIC_SSE_INTSH_P_RI : InstrItinClass;
    291 
    292 def IIC_SSE_INTSHDQ_P_RI : InstrItinClass;
    293 
    294 def IIC_SSE_SHUFP : InstrItinClass;
    295 def IIC_SSE_PSHUF_RI : InstrItinClass;
    296 def IIC_SSE_PSHUF_MI : InstrItinClass;
    297 
    298 def IIC_SSE_UNPCK : InstrItinClass;
    299 
    300 def IIC_SSE_MOVMSK : InstrItinClass;
    301 def IIC_SSE_MASKMOV : InstrItinClass;
    302 
    303 def IIC_SSE_PEXTRW : InstrItinClass;
    304 def IIC_SSE_PINSRW : InstrItinClass;
    305 
    306 def IIC_SSE_PABS_RR : InstrItinClass;
    307 def IIC_SSE_PABS_RM : InstrItinClass;
    308 
    309 def IIC_SSE_SQRTPS_RR : InstrItinClass;
    310 def IIC_SSE_SQRTPS_RM : InstrItinClass;
    311 def IIC_SSE_SQRTSS_RR : InstrItinClass;
    312 def IIC_SSE_SQRTSS_RM : InstrItinClass;
    313 def IIC_SSE_SQRTPD_RR : InstrItinClass;
    314 def IIC_SSE_SQRTPD_RM : InstrItinClass;
    315 def IIC_SSE_SQRTSD_RR : InstrItinClass;
    316 def IIC_SSE_SQRTSD_RM : InstrItinClass;
    317 
    318 def IIC_SSE_RSQRTPS_RR : InstrItinClass;
    319 def IIC_SSE_RSQRTPS_RM : InstrItinClass;
    320 def IIC_SSE_RSQRTSS_RR : InstrItinClass;
    321 def IIC_SSE_RSQRTSS_RM : InstrItinClass;
    322 
    323 def IIC_SSE_RCPP_RR : InstrItinClass;
    324 def IIC_SSE_RCPP_RM : InstrItinClass;
    325 def IIC_SSE_RCPS_RR : InstrItinClass;
    326 def IIC_SSE_RCPS_RM : InstrItinClass;
    327 
    328 def IIC_SSE_MOV_S_RR : InstrItinClass;
    329 def IIC_SSE_MOV_S_RM : InstrItinClass;
    330 def IIC_SSE_MOV_S_MR : InstrItinClass;
    331 
    332 def IIC_SSE_MOVA_P_RR : InstrItinClass;
    333 def IIC_SSE_MOVA_P_RM : InstrItinClass;
    334 def IIC_SSE_MOVA_P_MR : InstrItinClass;
    335 
    336 def IIC_SSE_MOVU_P_RR : InstrItinClass;
    337 def IIC_SSE_MOVU_P_RM : InstrItinClass;
    338 def IIC_SSE_MOVU_P_MR : InstrItinClass;
    339 
    340 def IIC_SSE_MOVDQ : InstrItinClass;
    341 def IIC_SSE_MOVD_ToGP : InstrItinClass;
    342 def IIC_SSE_MOVQ_RR : InstrItinClass;
    343 
    344 def IIC_SSE_MOV_LH : InstrItinClass;
    345 
    346 def IIC_SSE_LDDQU : InstrItinClass;
    347 
    348 def IIC_SSE_MOVNT : InstrItinClass;
    349 
    350 def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
    351 def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
    352 def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
    353 def IIC_SSE_PHADDSUBSW_RM : InstrItinClass;
    354 def IIC_SSE_PHADDSUBW_RR : InstrItinClass;
    355 def IIC_SSE_PHADDSUBW_RM : InstrItinClass;
    356 def IIC_SSE_PSHUFB_RR : InstrItinClass;
    357 def IIC_SSE_PSHUFB_RM : InstrItinClass;
    358 def IIC_SSE_PSIGN_RR : InstrItinClass;
    359 def IIC_SSE_PSIGN_RM : InstrItinClass;
    360 
    361 def IIC_SSE_PMADD : InstrItinClass;
    362 def IIC_SSE_PMULHRSW : InstrItinClass;
    363 def IIC_SSE_PALIGNRR : InstrItinClass;
    364 def IIC_SSE_PALIGNRM : InstrItinClass;
    365 def IIC_SSE_MWAIT : InstrItinClass;
    366 def IIC_SSE_MONITOR : InstrItinClass;
    367 def IIC_SSE_MWAITX : InstrItinClass;
    368 def IIC_SSE_MONITORX : InstrItinClass;
    369 
    370 def IIC_SSE_PREFETCH : InstrItinClass;
    371 def IIC_SSE_PAUSE : InstrItinClass;
    372 def IIC_SSE_LFENCE : InstrItinClass;
    373 def IIC_SSE_MFENCE : InstrItinClass;
    374 def IIC_SSE_SFENCE : InstrItinClass;
    375 def IIC_SSE_LDMXCSR : InstrItinClass;
    376 def IIC_SSE_STMXCSR : InstrItinClass;
    377 
    378 def IIC_SSE_CVT_PD_RR : InstrItinClass;
    379 def IIC_SSE_CVT_PD_RM : InstrItinClass;
    380 def IIC_SSE_CVT_PS_RR : InstrItinClass;
    381 def IIC_SSE_CVT_PS_RM : InstrItinClass;
    382 def IIC_SSE_CVT_PI2PS_RR : InstrItinClass;
    383 def IIC_SSE_CVT_PI2PS_RM : InstrItinClass;
    384 def IIC_SSE_CVT_Scalar_RR : InstrItinClass;
    385 def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
    386 def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
    387 def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
    388 def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
    389 def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
    390 def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
    391 def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
    392 
    393 // MMX
    394 def IIC_MMX_MOV_MM_RM : InstrItinClass;
    395 def IIC_MMX_MOV_REG_MM : InstrItinClass;
    396 def IIC_MMX_MOVQ_RM : InstrItinClass;
    397 def IIC_MMX_MOVQ_RR : InstrItinClass;
    398 
    399 def IIC_MMX_ALU_RM : InstrItinClass;
    400 def IIC_MMX_ALU_RR : InstrItinClass;
    401 def IIC_MMX_ALUQ_RM : InstrItinClass;
    402 def IIC_MMX_ALUQ_RR : InstrItinClass;
    403 def IIC_MMX_PHADDSUBW_RM : InstrItinClass;
    404 def IIC_MMX_PHADDSUBW_RR : InstrItinClass;
    405 def IIC_MMX_PHADDSUBD_RM : InstrItinClass;
    406 def IIC_MMX_PHADDSUBD_RR : InstrItinClass;
    407 def IIC_MMX_PMUL : InstrItinClass;
    408 def IIC_MMX_MISC_FUNC_MEM : InstrItinClass;
    409 def IIC_MMX_MISC_FUNC_REG : InstrItinClass;
    410 def IIC_MMX_PSADBW : InstrItinClass;
    411 def IIC_MMX_SHIFT_RI : InstrItinClass;
    412 def IIC_MMX_SHIFT_RM : InstrItinClass;
    413 def IIC_MMX_SHIFT_RR : InstrItinClass;
    414 def IIC_MMX_UNPCK_H_RM : InstrItinClass;
    415 def IIC_MMX_UNPCK_H_RR : InstrItinClass;
    416 def IIC_MMX_UNPCK_L : InstrItinClass;
    417 def IIC_MMX_PCK_RM : InstrItinClass;
    418 def IIC_MMX_PCK_RR : InstrItinClass;
    419 def IIC_MMX_PSHUF : InstrItinClass;
    420 def IIC_MMX_PEXTR : InstrItinClass;
    421 def IIC_MMX_PINSRW : InstrItinClass;
    422 def IIC_MMX_MASKMOV : InstrItinClass;
    423 
    424 def IIC_MMX_CVT_PD_RR : InstrItinClass;
    425 def IIC_MMX_CVT_PD_RM : InstrItinClass;
    426 def IIC_MMX_CVT_PS_RR : InstrItinClass;
    427 def IIC_MMX_CVT_PS_RM : InstrItinClass;
    428 
    429 def IIC_CMPX_LOCK : InstrItinClass;
    430 def IIC_CMPX_LOCK_8 : InstrItinClass;
    431 def IIC_CMPX_LOCK_8B : InstrItinClass;
    432 def IIC_CMPX_LOCK_16B : InstrItinClass;
    433 
    434 def IIC_XADD_LOCK_MEM : InstrItinClass;
    435 def IIC_XADD_LOCK_MEM8 : InstrItinClass;
    436 
    437 def IIC_FILD : InstrItinClass;
    438 def IIC_FLD : InstrItinClass;
    439 def IIC_FLD80 : InstrItinClass;
    440 def IIC_FST : InstrItinClass;
    441 def IIC_FST80 : InstrItinClass;
    442 def IIC_FIST : InstrItinClass;
    443 def IIC_FLDZ : InstrItinClass;
    444 def IIC_FUCOM : InstrItinClass;
    445 def IIC_FUCOMI : InstrItinClass;
    446 def IIC_FCOMI : InstrItinClass;
    447 def IIC_FNSTSW : InstrItinClass;
    448 def IIC_FNSTCW : InstrItinClass;
    449 def IIC_FLDCW : InstrItinClass;
    450 def IIC_FNINIT : InstrItinClass;
    451 def IIC_FFREE : InstrItinClass;
    452 def IIC_FNCLEX : InstrItinClass;
    453 def IIC_WAIT : InstrItinClass;
    454 def IIC_FXAM : InstrItinClass;
    455 def IIC_FNOP : InstrItinClass;
    456 def IIC_FLDL : InstrItinClass;
    457 def IIC_F2XM1 : InstrItinClass;
    458 def IIC_FYL2X : InstrItinClass;
    459 def IIC_FPTAN : InstrItinClass;
    460 def IIC_FPATAN : InstrItinClass;
    461 def IIC_FXTRACT : InstrItinClass;
    462 def IIC_FPREM1 : InstrItinClass;
    463 def IIC_FPSTP : InstrItinClass;
    464 def IIC_FPREM : InstrItinClass;
    465 def IIC_FYL2XP1 : InstrItinClass;
    466 def IIC_FSINCOS : InstrItinClass;
    467 def IIC_FRNDINT : InstrItinClass;
    468 def IIC_FSCALE : InstrItinClass;
    469 def IIC_FCOMPP : InstrItinClass;
    470 def IIC_FXSAVE : InstrItinClass;
    471 def IIC_FXRSTOR : InstrItinClass;
    472 
    473 def IIC_FXCH : InstrItinClass;
    474 
    475 // System instructions
    476 def IIC_CPUID : InstrItinClass;
    477 def IIC_INT : InstrItinClass;
    478 def IIC_INT3 : InstrItinClass;
    479 def IIC_INVD : InstrItinClass;
    480 def IIC_INVLPG : InstrItinClass;
    481 def IIC_IRET : InstrItinClass;
    482 def IIC_HLT : InstrItinClass;
    483 def IIC_LXS : InstrItinClass;
    484 def IIC_LTR : InstrItinClass;
    485 def IIC_RDTSC : InstrItinClass;
    486 def IIC_RSM : InstrItinClass;
    487 def IIC_SIDT : InstrItinClass;
    488 def IIC_SGDT : InstrItinClass;
    489 def IIC_SLDT : InstrItinClass;
    490 def IIC_STR : InstrItinClass;
    491 def IIC_SWAPGS : InstrItinClass;
    492 def IIC_SYSCALL : InstrItinClass;
    493 def IIC_SYS_ENTER_EXIT : InstrItinClass;
    494 def IIC_IN_RR : InstrItinClass;
    495 def IIC_IN_RI : InstrItinClass;
    496 def IIC_OUT_RR : InstrItinClass;
    497 def IIC_OUT_IR : InstrItinClass;
    498 def IIC_INS : InstrItinClass;
    499 def IIC_MOV_REG_DR : InstrItinClass;
    500 def IIC_MOV_DR_REG : InstrItinClass;
    501 def IIC_MOV_REG_CR : InstrItinClass;
    502 def IIC_MOV_CR_REG : InstrItinClass;
    503 def IIC_MOV_REG_SR : InstrItinClass;
    504 def IIC_MOV_MEM_SR : InstrItinClass;
    505 def IIC_MOV_SR_REG : InstrItinClass;
    506 def IIC_MOV_SR_MEM : InstrItinClass;
    507 def IIC_LAR_RM : InstrItinClass;
    508 def IIC_LAR_RR : InstrItinClass;
    509 def IIC_LSL_RM : InstrItinClass;
    510 def IIC_LSL_RR : InstrItinClass;
    511 def IIC_LGDT : InstrItinClass;
    512 def IIC_LIDT : InstrItinClass;
    513 def IIC_LLDT_REG : InstrItinClass;
    514 def IIC_LLDT_MEM : InstrItinClass;
    515 def IIC_PUSH_CS : InstrItinClass;
    516 def IIC_PUSH_SR : InstrItinClass;
    517 def IIC_POP_SR : InstrItinClass;
    518 def IIC_POP_SR_SS : InstrItinClass;
    519 def IIC_VERR : InstrItinClass;
    520 def IIC_VERW_REG : InstrItinClass;
    521 def IIC_VERW_MEM : InstrItinClass;
    522 def IIC_WRMSR : InstrItinClass;
    523 def IIC_RDMSR : InstrItinClass;
    524 def IIC_RDPMC : InstrItinClass;
    525 def IIC_SMSW : InstrItinClass;
    526 def IIC_LMSW_REG : InstrItinClass;
    527 def IIC_LMSW_MEM : InstrItinClass;
    528 def IIC_ENTER : InstrItinClass;
    529 def IIC_LEAVE : InstrItinClass;
    530 def IIC_POP_MEM : InstrItinClass;
    531 def IIC_POP_REG16 : InstrItinClass;
    532 def IIC_POP_REG : InstrItinClass;
    533 def IIC_POP_F : InstrItinClass;
    534 def IIC_POP_FD : InstrItinClass;
    535 def IIC_POP_A : InstrItinClass;
    536 def IIC_PUSH_IMM : InstrItinClass;
    537 def IIC_PUSH_MEM : InstrItinClass;
    538 def IIC_PUSH_REG : InstrItinClass;
    539 def IIC_PUSH_F : InstrItinClass;
    540 def IIC_PUSH_A : InstrItinClass;
    541 def IIC_BSWAP : InstrItinClass;
    542 def IIC_BIT_SCAN_MEM : InstrItinClass;
    543 def IIC_BIT_SCAN_REG : InstrItinClass;
    544 def IIC_MOVS : InstrItinClass;
    545 def IIC_STOS : InstrItinClass;
    546 def IIC_SCAS : InstrItinClass;
    547 def IIC_CMPS : InstrItinClass;
    548 def IIC_MOV : InstrItinClass;
    549 def IIC_MOV_MEM : InstrItinClass;
    550 def IIC_AHF : InstrItinClass;
    551 def IIC_BT_MI : InstrItinClass;
    552 def IIC_BT_MR : InstrItinClass;
    553 def IIC_BT_RI : InstrItinClass;
    554 def IIC_BT_RR : InstrItinClass;
    555 def IIC_BTX_MI : InstrItinClass;
    556 def IIC_BTX_MR : InstrItinClass;
    557 def IIC_BTX_RI : InstrItinClass;
    558 def IIC_BTX_RR : InstrItinClass;
    559 def IIC_XCHG_REG : InstrItinClass;
    560 def IIC_XCHG_MEM : InstrItinClass;
    561 def IIC_XADD_REG : InstrItinClass;
    562 def IIC_XADD_MEM : InstrItinClass;
    563 def IIC_CMPXCHG_MEM : InstrItinClass;
    564 def IIC_CMPXCHG_REG : InstrItinClass;
    565 def IIC_CMPXCHG_MEM8 : InstrItinClass;
    566 def IIC_CMPXCHG_REG8 : InstrItinClass;
    567 def IIC_CMPXCHG_8B : InstrItinClass;
    568 def IIC_CMPXCHG_16B : InstrItinClass;
    569 def IIC_LODS : InstrItinClass;
    570 def IIC_OUTS : InstrItinClass;
    571 def IIC_CLC : InstrItinClass;
    572 def IIC_CLD : InstrItinClass;
    573 def IIC_CLI : InstrItinClass;
    574 def IIC_CMC : InstrItinClass;
    575 def IIC_CLTS : InstrItinClass;
    576 def IIC_STC : InstrItinClass;
    577 def IIC_STI : InstrItinClass;
    578 def IIC_STD : InstrItinClass;
    579 def IIC_XLAT : InstrItinClass;
    580 def IIC_AAA : InstrItinClass;
    581 def IIC_AAD : InstrItinClass;
    582 def IIC_AAM : InstrItinClass;
    583 def IIC_AAS : InstrItinClass;
    584 def IIC_DAA : InstrItinClass;
    585 def IIC_DAS : InstrItinClass;
    586 def IIC_BOUND : InstrItinClass;
    587 def IIC_ARPL_REG : InstrItinClass;
    588 def IIC_ARPL_MEM : InstrItinClass;
    589 def IIC_MOVBE : InstrItinClass;
    590 def IIC_AES   : InstrItinClass;
    591 def IIC_BLEND_MEM : InstrItinClass;
    592 def IIC_BLEND_NOMEM : InstrItinClass;
    593 def IIC_CBW   : InstrItinClass;
    594 def IIC_CRC32_REG : InstrItinClass;
    595 def IIC_CRC32_MEM : InstrItinClass;
    596 def IIC_SSE_DPPD_RR : InstrItinClass;
    597 def IIC_SSE_DPPD_RM : InstrItinClass;
    598 def IIC_SSE_DPPS_RR : InstrItinClass;
    599 def IIC_SSE_DPPS_RM : InstrItinClass;
    600 def IIC_MMX_EMMS : InstrItinClass;
    601 def IIC_SSE_EXTRACTPS_RR : InstrItinClass;
    602 def IIC_SSE_EXTRACTPS_RM : InstrItinClass;
    603 def IIC_SSE_INSERTPS_RR : InstrItinClass;
    604 def IIC_SSE_INSERTPS_RM : InstrItinClass;
    605 def IIC_SSE_MPSADBW_RR : InstrItinClass;
    606 def IIC_SSE_MPSADBW_RM : InstrItinClass;
    607 def IIC_SSE_PMULLD_RR : InstrItinClass;
    608 def IIC_SSE_PMULLD_RM : InstrItinClass;
    609 def IIC_SSE_ROUNDPS_REG : InstrItinClass;
    610 def IIC_SSE_ROUNDPS_MEM : InstrItinClass;
    611 def IIC_SSE_ROUNDPD_REG : InstrItinClass;
    612 def IIC_SSE_ROUNDPD_MEM : InstrItinClass;
    613 def IIC_SSE_POPCNT_RR : InstrItinClass;
    614 def IIC_SSE_POPCNT_RM : InstrItinClass;
    615 def IIC_SSE_PCLMULQDQ_RR : InstrItinClass;
    616 def IIC_SSE_PCLMULQDQ_RM : InstrItinClass;
    617 
    618 def IIC_NOP : InstrItinClass;
    619 
    620 //===----------------------------------------------------------------------===//
    621 // Processor instruction itineraries.
    622 
    623 // IssueWidth is analogous to the number of decode units. Core and its
    624 // descendents, including Nehalem and SandyBridge have 4 decoders.
    625 // Resources beyond the decoder operate on micro-ops and are bufferred
    626 // so adjacent micro-ops don't directly compete.
    627 //
    628 // MicroOpBufferSize > 1 indicates that RAW dependencies can be
    629 // decoded in the same cycle. The value 32 is a reasonably arbitrary
    630 // number of in-flight instructions.
    631 //
    632 // HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
    633 // indicates high latency opcodes. Alternatively, InstrItinData
    634 // entries may be included here to define specific operand
    635 // latencies. Since these latencies are not used for pipeline hazards,
    636 // they do not need to be exact.
    637 //
    638 // The GenericX86Model contains no instruction itineraries
    639 // and disables PostRAScheduler.
    640 class GenericX86Model : SchedMachineModel {
    641   let IssueWidth = 4;
    642   let MicroOpBufferSize = 32;
    643   let LoadLatency = 4;
    644   let HighLatency = 10;
    645   let PostRAScheduler = 0;
    646   let CompleteModel = 0;
    647 }
    648 
    649 def GenericModel : GenericX86Model;
    650 
    651 // Define a model with the PostRAScheduler enabled.
    652 def GenericPostRAModel : GenericX86Model {
    653   let PostRAScheduler = 1;
    654 }
    655 
    656 include "X86ScheduleAtom.td"
    657 include "X86SchedSandyBridge.td"
    658 include "X86SchedHaswell.td"
    659 include "X86ScheduleSLM.td"
    660 include "X86ScheduleBtVer2.td"
    661 
    662