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      1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the X86 specific subclass of TargetMachine.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "X86TargetMachine.h"
     15 #include "X86.h"
     16 #include "X86TargetObjectFile.h"
     17 #include "X86TargetTransformInfo.h"
     18 #include "llvm/CodeGen/Passes.h"
     19 #include "llvm/CodeGen/TargetPassConfig.h"
     20 #include "llvm/IR/Function.h"
     21 #include "llvm/IR/LegacyPassManager.h"
     22 #include "llvm/Support/CommandLine.h"
     23 #include "llvm/Support/FormattedStream.h"
     24 #include "llvm/Support/TargetRegistry.h"
     25 #include "llvm/Target/TargetOptions.h"
     26 using namespace llvm;
     27 
     28 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
     29                                cl::desc("Enable the machine combiner pass"),
     30                                cl::init(true), cl::Hidden);
     31 
     32 namespace llvm {
     33 void initializeWinEHStatePassPass(PassRegistry &);
     34 }
     35 
     36 extern "C" void LLVMInitializeX86Target() {
     37   // Register the target.
     38   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
     39   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
     40 
     41   PassRegistry &PR = *PassRegistry::getPassRegistry();
     42   initializeWinEHStatePassPass(PR);
     43   initializeFixupBWInstPassPass(PR);
     44 }
     45 
     46 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
     47   if (TT.isOSBinFormatMachO()) {
     48     if (TT.getArch() == Triple::x86_64)
     49       return make_unique<X86_64MachoTargetObjectFile>();
     50     return make_unique<TargetLoweringObjectFileMachO>();
     51   }
     52 
     53   if (TT.isOSLinux() || TT.isOSNaCl())
     54     return make_unique<X86LinuxNaClTargetObjectFile>();
     55   if (TT.isOSBinFormatELF())
     56     return make_unique<X86ELFTargetObjectFile>();
     57   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
     58     return make_unique<X86WindowsTargetObjectFile>();
     59   if (TT.isOSBinFormatCOFF())
     60     return make_unique<TargetLoweringObjectFileCOFF>();
     61   llvm_unreachable("unknown subtarget type");
     62 }
     63 
     64 static std::string computeDataLayout(const Triple &TT) {
     65   // X86 is little endian
     66   std::string Ret = "e";
     67 
     68   Ret += DataLayout::getManglingComponent(TT);
     69   // X86 and x32 have 32 bit pointers.
     70   if ((TT.isArch64Bit() &&
     71        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
     72       !TT.isArch64Bit())
     73     Ret += "-p:32:32";
     74 
     75   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
     76   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
     77     Ret += "-i64:64";
     78   else if (TT.isOSIAMCU())
     79     Ret += "-i64:32-f64:32";
     80   else
     81     Ret += "-f64:32:64";
     82 
     83   // Some ABIs align long double to 128 bits, others to 32.
     84   if (TT.isOSNaCl() || TT.isOSIAMCU())
     85     ; // No f80
     86   else if (TT.isArch64Bit() || TT.isOSDarwin())
     87     Ret += "-f80:128";
     88   else
     89     Ret += "-f80:32";
     90 
     91   if (TT.isOSIAMCU())
     92     Ret += "-f128:32";
     93 
     94   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
     95   if (TT.isArch64Bit())
     96     Ret += "-n8:16:32:64";
     97   else
     98     Ret += "-n8:16:32";
     99 
    100   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
    101   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
    102     Ret += "-a:0:32-S32";
    103   else
    104     Ret += "-S128";
    105 
    106   return Ret;
    107 }
    108 
    109 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
    110                                            Optional<Reloc::Model> RM) {
    111   bool is64Bit = TT.getArch() == Triple::x86_64;
    112   if (!RM.hasValue()) {
    113     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
    114     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
    115     // use static relocation model by default.
    116     if (TT.isOSDarwin()) {
    117       if (is64Bit)
    118         return Reloc::PIC_;
    119       return Reloc::DynamicNoPIC;
    120     }
    121     if (TT.isOSWindows() && is64Bit)
    122       return Reloc::PIC_;
    123     return Reloc::Static;
    124   }
    125 
    126   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
    127   // is defined as a model for code which may be used in static or dynamic
    128   // executables but not necessarily a shared library. On X86-32 we just
    129   // compile in -static mode, in x86-64 we use PIC.
    130   if (*RM == Reloc::DynamicNoPIC) {
    131     if (is64Bit)
    132       return Reloc::PIC_;
    133     if (!TT.isOSDarwin())
    134       return Reloc::Static;
    135   }
    136 
    137   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
    138   // the Mach-O file format doesn't support it.
    139   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
    140     return Reloc::PIC_;
    141 
    142   return *RM;
    143 }
    144 
    145 /// Create an X86 target.
    146 ///
    147 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
    148                                    StringRef CPU, StringRef FS,
    149                                    const TargetOptions &Options,
    150                                    Optional<Reloc::Model> RM,
    151                                    CodeModel::Model CM, CodeGenOpt::Level OL)
    152     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
    153                         getEffectiveRelocModel(TT, RM), CM, OL),
    154       TLOF(createTLOF(getTargetTriple())),
    155       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
    156   // Windows stack unwinder gets confused when execution flow "falls through"
    157   // after a call to 'noreturn' function.
    158   // To prevent that, we emit a trap for 'unreachable' IR instructions.
    159   // (which on X86, happens to be the 'ud2' instruction)
    160   // On PS4, the "return address" of a 'noreturn' call must still be within
    161   // the calling function, and TrapUnreachable is an easy way to get that.
    162   if (Subtarget.isTargetWin64() || Subtarget.isTargetPS4())
    163     this->Options.TrapUnreachable = true;
    164 
    165   // By default (and when -ffast-math is on), enable estimate codegen for
    166   // everything except scalar division. By default, use 1 refinement step for
    167   // all operations. Defaults may be overridden by using command-line options.
    168   // Scalar division estimates are disabled because they break too much
    169   // real-world code. These defaults match GCC behavior.
    170   this->Options.Reciprocals.setDefaults("sqrtf", true, 1);
    171   this->Options.Reciprocals.setDefaults("divf", false, 1);
    172   this->Options.Reciprocals.setDefaults("vec-sqrtf", true, 1);
    173   this->Options.Reciprocals.setDefaults("vec-divf", true, 1);
    174 
    175   initAsmInfo();
    176 }
    177 
    178 X86TargetMachine::~X86TargetMachine() {}
    179 
    180 const X86Subtarget *
    181 X86TargetMachine::getSubtargetImpl(const Function &F) const {
    182   Attribute CPUAttr = F.getFnAttribute("target-cpu");
    183   Attribute FSAttr = F.getFnAttribute("target-features");
    184 
    185   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
    186                       ? CPUAttr.getValueAsString()
    187                       : (StringRef)TargetCPU;
    188   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
    189                      ? FSAttr.getValueAsString()
    190                      : (StringRef)TargetFS;
    191 
    192   SmallString<512> Key;
    193   Key.reserve(CPU.size() + FS.size());
    194   Key += CPU;
    195   Key += FS;
    196 
    197   // FIXME: This is related to the code below to reset the target options,
    198   // we need to know whether or not the soft float flag is set on the
    199   // function before we can generate a subtarget. We also need to use
    200   // it as a key for the subtarget since that can be the only difference
    201   // between two functions.
    202   bool SoftFloat =
    203       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
    204   // If the soft float attribute is set on the function turn on the soft float
    205   // subtarget feature.
    206   if (SoftFloat)
    207     Key += FS.empty() ? "+soft-float" : ",+soft-float";
    208 
    209   FS = Key.substr(CPU.size());
    210 
    211   auto &I = SubtargetMap[Key];
    212   if (!I) {
    213     // This needs to be done before we create a new subtarget since any
    214     // creation will depend on the TM and the code generation flags on the
    215     // function that reside in TargetOptions.
    216     resetTargetOptions(F);
    217     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
    218                                         Options.StackAlignmentOverride);
    219   }
    220   return I.get();
    221 }
    222 
    223 //===----------------------------------------------------------------------===//
    224 // Command line options for x86
    225 //===----------------------------------------------------------------------===//
    226 static cl::opt<bool>
    227 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
    228   cl::desc("Minimize AVX to SSE transition penalty"),
    229   cl::init(true));
    230 
    231 //===----------------------------------------------------------------------===//
    232 // X86 TTI query.
    233 //===----------------------------------------------------------------------===//
    234 
    235 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
    236   return TargetIRAnalysis([this](const Function &F) {
    237     return TargetTransformInfo(X86TTIImpl(this, F));
    238   });
    239 }
    240 
    241 
    242 //===----------------------------------------------------------------------===//
    243 // Pass Pipeline Configuration
    244 //===----------------------------------------------------------------------===//
    245 
    246 namespace {
    247 /// X86 Code Generator Pass Configuration Options.
    248 class X86PassConfig : public TargetPassConfig {
    249 public:
    250   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
    251     : TargetPassConfig(TM, PM) {}
    252 
    253   X86TargetMachine &getX86TargetMachine() const {
    254     return getTM<X86TargetMachine>();
    255   }
    256 
    257   void addIRPasses() override;
    258   bool addInstSelector() override;
    259   bool addILPOpts() override;
    260   bool addPreISel() override;
    261   void addPreRegAlloc() override;
    262   void addPostRegAlloc() override;
    263   void addPreEmitPass() override;
    264   void addPreSched2() override;
    265 };
    266 } // namespace
    267 
    268 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
    269   return new X86PassConfig(this, PM);
    270 }
    271 
    272 void X86PassConfig::addIRPasses() {
    273   addPass(createAtomicExpandPass(&getX86TargetMachine()));
    274 
    275   TargetPassConfig::addIRPasses();
    276 }
    277 
    278 bool X86PassConfig::addInstSelector() {
    279   // Install an instruction selector.
    280   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
    281 
    282   // For ELF, cleanup any local-dynamic TLS accesses.
    283   if (TM->getTargetTriple().isOSBinFormatELF() &&
    284       getOptLevel() != CodeGenOpt::None)
    285     addPass(createCleanupLocalDynamicTLSPass());
    286 
    287   addPass(createX86GlobalBaseRegPass());
    288   return false;
    289 }
    290 
    291 bool X86PassConfig::addILPOpts() {
    292   addPass(&EarlyIfConverterID);
    293   if (EnableMachineCombinerPass)
    294     addPass(&MachineCombinerID);
    295   return true;
    296 }
    297 
    298 bool X86PassConfig::addPreISel() {
    299   // Only add this pass for 32-bit x86 Windows.
    300   const Triple &TT = TM->getTargetTriple();
    301   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
    302     addPass(createX86WinEHStatePass());
    303   return true;
    304 }
    305 
    306 void X86PassConfig::addPreRegAlloc() {
    307   if (getOptLevel() != CodeGenOpt::None) {
    308     addPass(createX86FixupSetCC());
    309     addPass(createX86OptimizeLEAs());
    310     addPass(createX86CallFrameOptimization());
    311   }
    312 
    313   addPass(createX86WinAllocaExpander());
    314 }
    315 
    316 void X86PassConfig::addPostRegAlloc() {
    317   addPass(createX86FloatingPointStackifierPass());
    318 }
    319 
    320 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
    321 
    322 void X86PassConfig::addPreEmitPass() {
    323   if (getOptLevel() != CodeGenOpt::None)
    324     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
    325 
    326   if (UseVZeroUpper)
    327     addPass(createX86IssueVZeroUpperPass());
    328 
    329   if (getOptLevel() != CodeGenOpt::None) {
    330     addPass(createX86FixupBWInsts());
    331     addPass(createX86PadShortFunctions());
    332     addPass(createX86FixupLEAs());
    333   }
    334 }
    335