1 ; RUN: llc -O3 -aarch64-gep-opt=true -print-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck <%t %s 2 ; REQUIRES: asserts 3 target triple = "aarch64--linux-android" 4 5 %typeD = type { i32, i32, [256 x i32], [257 x i32] } 6 7 ; Function Attrs: noreturn nounwind uwtable 8 define i32 @test1(%typeD* nocapture %s) { 9 entry: 10 ; CHECK-LABEL: entry: 11 ; CHECK: %uglygep = getelementptr i8, i8* %0, i64 1032 12 ; CHECK: br label %do.body.i 13 14 15 %tPos = getelementptr inbounds %typeD, %typeD* %s, i64 0, i32 0 16 %k0 = getelementptr inbounds %typeD, %typeD* %s, i64 0, i32 1 17 %.pre = load i32, i32* %tPos, align 4 18 br label %do.body.i 19 20 do.body.i: 21 ; CHECK-LABEL: do.body.i: 22 ; CHECK: %uglygep2 = getelementptr i8, i8* %uglygep, i64 %3 23 ; CHECK-NEXT: %4 = bitcast i8* %uglygep2 to i32* 24 ; CHECK-NOT: %uglygep2 = getelementptr i8, i8* %uglygep, i64 1032 25 26 27 %0 = phi i32 [ 256, %entry ], [ %.be, %do.body.i.backedge ] 28 %1 = phi i32 [ 0, %entry ], [ %.be6, %do.body.i.backedge ] 29 %add.i = add nsw i32 %1, %0 30 %shr.i = ashr i32 %add.i, 1 31 %idxprom.i = sext i32 %shr.i to i64 32 %arrayidx.i = getelementptr inbounds %typeD, %typeD* %s, i64 0, i32 3, i64 %idxprom.i 33 %2 = load i32, i32* %arrayidx.i, align 4 34 %cmp.i = icmp sle i32 %2, %.pre 35 %na.1.i = select i1 %cmp.i, i32 %0, i32 %shr.i 36 %nb.1.i = select i1 %cmp.i, i32 %shr.i, i32 %1 37 %sub.i = sub nsw i32 %na.1.i, %nb.1.i 38 %cmp1.i = icmp eq i32 %sub.i, 1 39 br i1 %cmp1.i, label %fooo.exit, label %do.body.i.backedge 40 41 do.body.i.backedge: 42 %.be = phi i32 [ %na.1.i, %do.body.i ], [ 256, %fooo.exit ] 43 %.be6 = phi i32 [ %nb.1.i, %do.body.i ], [ 0, %fooo.exit ] 44 br label %do.body.i 45 46 fooo.exit: ; preds = %do.body.i 47 store i32 %nb.1.i, i32* %k0, align 4 48 br label %do.body.i.backedge 49 } 50 51
