1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s 2 ; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll 3 4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type 5 ; is illegal in AArch64 backend, the legalizer tries to scalarize this node. 6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized. 7 ; Currently the type legalizer will have an assertion failure as it assumes all 8 ; operands of SETCC have been legalized. 9 ; FIXME: If the algorithm of type scalarization is improved and can legaize 10 ; "v1i1 SETCC" correctly, these test cases are not needed. 11 12 define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) { 13 ; CHECK-LABEL: test_sext_extr_cmp_0: 14 ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}} 15 %1 = icmp sge <1 x i64> %v1, %v2 16 %2 = extractelement <1 x i1> %1, i32 0 17 %vget_lane = sext i1 %2 to i64 18 ret i64 %vget_lane 19 } 20 21 define i64 @test_sext_extr_cmp_1(<1 x double> %v1, <1 x double> %v2) { 22 ; CHECK-LABEL: test_sext_extr_cmp_1: 23 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}} 24 %1 = fcmp oeq <1 x double> %v1, %v2 25 %2 = extractelement <1 x i1> %1, i32 0 26 %vget_lane = sext i1 %2 to i64 27 ret i64 %vget_lane 28 } 29 30 define <1 x i64> @test_select_v1i1_0(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) { 31 ; CHECK-LABEL: test_select_v1i1_0: 32 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 33 ; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b 34 %1 = icmp eq <1 x i64> %v1, %v2 35 %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3 36 ret <1 x i64> %res 37 } 38 39 define <1 x i64> @test_select_v1i1_1(<1 x double> %v1, <1 x double> %v2, <1 x i64> %v3) { 40 ; CHECK-LABEL: test_select_v1i1_1: 41 ; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 42 ; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b 43 %1 = fcmp oeq <1 x double> %v1, %v2 44 %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3 45 ret <1 x i64> %res 46 } 47 48 define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x double> %v3) { 49 ; CHECK-LABEL: test_select_v1i1_2: 50 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 51 ; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b 52 %1 = icmp eq <1 x i64> %v1, %v2 53 %res = select <1 x i1> %1, <1 x double> zeroinitializer, <1 x double> %v3 54 ret <1 x double> %res 55 } 56 57 define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) { 58 ; CHECK-LABEL: test_br_extr_cmp: 59 ; CHECK: cmp x{{[0-9]+}}, x{{[0-9]+}} 60 %1 = icmp eq <1 x i64> %v1, %v2 61 %2 = extractelement <1 x i1> %1, i32 0 62 br i1 %2, label %if.end, label %if.then 63 64 if.then: 65 ret i32 0; 66 67 if.end: 68 ret i32 1; 69 } 70
