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      1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
      2 
      3 ; Check that building up a vector w/ only one non-zero lane initializes
      4 ; intelligently.
      5 define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
      6 ; CHECK-LABEL: one_lane:
      7 ; CHECK: dup.16b v[[REG:[0-9]+]], wzr
      8 ; CHECK-NEXT: ins.b v[[REG]][0], w1
      9 ; v and q are aliases, and str is preferred against st.16b when possible
     10 ; rdar://11246289
     11 ; CHECK: str q[[REG]], [x0]
     12 ; CHECK: ret
     13   %conv = trunc i32 %skip0 to i8
     14   %vset_lane = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv, i32 0
     15   %tmp = bitcast i32* %out_int to <4 x i32>*
     16   %tmp1 = bitcast <16 x i8> %vset_lane to <4 x i32>
     17   store <4 x i32> %tmp1, <4 x i32>* %tmp, align 16
     18   ret void
     19 }
     20 
     21 ; Check that building a vector from floats doesn't insert an unnecessary
     22 ; copy for lane zero.
     23 define <4 x float>  @foo(float %a, float %b, float %c, float %d) nounwind {
     24 ; CHECK-LABEL: foo:
     25 ; CHECK-NOT: ins.s v0[0], v0[0]
     26 ; CHECK: ins.s v0[1], v1[0]
     27 ; CHECK: ins.s v0[2], v2[0]
     28 ; CHECK: ins.s v0[3], v3[0]
     29 ; CHECK: ret
     30   %1 = insertelement <4 x float> undef, float %a, i32 0
     31   %2 = insertelement <4 x float> %1, float %b, i32 1
     32   %3 = insertelement <4 x float> %2, float %c, i32 2
     33   %4 = insertelement <4 x float> %3, float %d, i32 3
     34   ret <4 x float> %4
     35 }
     36 
     37 define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
     38 ; CHECK-LABEL: build_all_zero:
     39 ; CHECK: mov	w[[GREG:[0-9]+]], #44672
     40 ; CHECK-NEXT:	fmov	s[[FREG:[0-9]+]], w[[GREG]]
     41 ; CHECK-NEXT:	mul.8h	v0, v0, v[[FREG]]
     42   %b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
     43   %c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
     44   ret <8 x i16> %c
     45 }
     46 
     47 ; There is an optimization in DAG Combiner as following:
     48 ;   fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
     49 ;        -> (BUILD_VECTOR A, B, ..., C, D, ...)
     50 ; This case checks when A,B and C,D are different types, there should be no
     51 ; assertion failure.
     52 define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) {
     53 ; CHECK-LABEL: concat_2_build_vector:
     54 ; CHECK: movi
     55   %vshl_n = shl <4 x i16> %in0, <i16 8, i16 8, i16 8, i16 8>
     56   %vshl_n2 = shl <4 x i16> %vshl_n, <i16 9, i16 9, i16 9, i16 9>
     57   %shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
     58   ret <8 x i16> %shuffle.i
     59 }
     60