1 ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s 2 3 define i32 @icmp_eq_imm(i32 %a) nounwind ssp { 4 entry: 5 ; CHECK-LABEL: icmp_eq_imm 6 ; CHECK: cmp w0, #31 7 ; CHECK-NEXT: cset w0, eq 8 %cmp = icmp eq i32 %a, 31 9 %conv = zext i1 %cmp to i32 10 ret i32 %conv 11 } 12 13 define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp { 14 entry: 15 ; CHECK-LABEL: icmp_eq_neg_imm 16 ; CHECK: cmn w0, #7 17 ; CHECK-NEXT: cset w0, eq 18 %cmp = icmp eq i32 %a, -7 19 %conv = zext i1 %cmp to i32 20 ret i32 %conv 21 } 22 23 define i32 @icmp_eq_i32(i32 %a, i32 %b) nounwind ssp { 24 entry: 25 ; CHECK-LABEL: icmp_eq_i32 26 ; CHECK: cmp w0, w1 27 ; CHECK-NEXT: cset w0, eq 28 %cmp = icmp eq i32 %a, %b 29 %conv = zext i1 %cmp to i32 30 ret i32 %conv 31 } 32 33 define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp { 34 entry: 35 ; CHECK-LABEL: icmp_ne 36 ; CHECK: cmp w0, w1 37 ; CHECK-NEXT: cset w0, ne 38 %cmp = icmp ne i32 %a, %b 39 %conv = zext i1 %cmp to i32 40 ret i32 %conv 41 } 42 43 define i32 @icmp_eq_ptr(i8* %a) { 44 entry: 45 ; CHECK-LABEL: icmp_eq_ptr 46 ; CHECK: cmp x0, #0 47 ; CHECK-NEXT: cset {{.+}}, eq 48 %cmp = icmp eq i8* %a, null 49 %conv = zext i1 %cmp to i32 50 ret i32 %conv 51 } 52 53 define i32 @icmp_ne_ptr(i8* %a) { 54 entry: 55 ; CHECK-LABEL: icmp_ne_ptr 56 ; CHECK: cmp x0, #0 57 ; CHECK-NEXT: cset {{.+}}, ne 58 %cmp = icmp ne i8* %a, null 59 %conv = zext i1 %cmp to i32 60 ret i32 %conv 61 } 62 63 define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp { 64 entry: 65 ; CHECK-LABEL: icmp_ugt 66 ; CHECK: cmp w0, w1 67 ; CHECK-NEXT: cset w0, hi 68 %cmp = icmp ugt i32 %a, %b 69 %conv = zext i1 %cmp to i32 70 ret i32 %conv 71 } 72 73 define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp { 74 entry: 75 ; CHECK-LABEL: icmp_uge 76 ; CHECK: cmp w0, w1 77 ; CHECK-NEXT: cset w0, hs 78 %cmp = icmp uge i32 %a, %b 79 %conv = zext i1 %cmp to i32 80 ret i32 %conv 81 } 82 83 define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp { 84 entry: 85 ; CHECK-LABEL: icmp_ult 86 ; CHECK: cmp w0, w1 87 ; CHECK-NEXT: cset w0, lo 88 %cmp = icmp ult i32 %a, %b 89 %conv = zext i1 %cmp to i32 90 ret i32 %conv 91 } 92 93 define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp { 94 entry: 95 ; CHECK-LABEL: icmp_ule 96 ; CHECK: cmp w0, w1 97 ; CHECK-NEXT: cset w0, ls 98 %cmp = icmp ule i32 %a, %b 99 %conv = zext i1 %cmp to i32 100 ret i32 %conv 101 } 102 103 define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp { 104 entry: 105 ; CHECK-LABEL: icmp_sgt 106 ; CHECK: cmp w0, w1 107 ; CHECK-NEXT: cset w0, gt 108 %cmp = icmp sgt i32 %a, %b 109 %conv = zext i1 %cmp to i32 110 ret i32 %conv 111 } 112 113 define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp { 114 entry: 115 ; CHECK-LABEL: icmp_sge 116 ; CHECK: cmp w0, w1 117 ; CHECK-NEXT: cset w0, ge 118 %cmp = icmp sge i32 %a, %b 119 %conv = zext i1 %cmp to i32 120 ret i32 %conv 121 } 122 123 define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp { 124 entry: 125 ; CHECK-LABEL: icmp_slt 126 ; CHECK: cmp w0, w1 127 ; CHECK-NEXT: cset w0, lt 128 %cmp = icmp slt i32 %a, %b 129 %conv = zext i1 %cmp to i32 130 ret i32 %conv 131 } 132 133 define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp { 134 entry: 135 ; CHECK-LABEL: icmp_sle 136 ; CHECK: cmp w0, w1 137 ; CHECK-NEXT: cset w0, le 138 %cmp = icmp sle i32 %a, %b 139 %conv = zext i1 %cmp to i32 140 ret i32 %conv 141 } 142 143 define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp { 144 entry: 145 ; CHECK-LABEL: icmp_i64 146 ; CHECK: cmp x0, x1 147 ; CHECK-NEXT: cset w{{[0-9]+}}, le 148 %cmp = icmp sle i64 %a, %b 149 %conv = zext i1 %cmp to i32 150 ret i32 %conv 151 } 152 153 define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp { 154 entry: 155 ; CHECK-LABEL: icmp_eq_i16 156 ; CHECK: sxth w0, w0 157 ; CHECK: cmp w0, w1, sxth 158 ; CHECK-NEXT: cset w0, eq 159 %cmp = icmp eq i16 %a, %b 160 ret i1 %cmp 161 } 162 163 define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp { 164 entry: 165 ; CHECK-LABEL: icmp_eq_i8 166 ; CHECK: sxtb w0, w0 167 ; CHECK-NEXT: cmp w0, w1, sxtb 168 ; CHECK-NEXT: cset w0, eq 169 %cmp = icmp eq i8 %a, %b 170 ret i1 %cmp 171 } 172 173 define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { 174 entry: 175 ; CHECK-LABEL: icmp_i16_unsigned 176 ; CHECK: uxth w0, w0 177 ; CHECK-NEXT: cmp w0, w1, uxth 178 ; CHECK-NEXT: cset w0, lo 179 %cmp = icmp ult i16 %a, %b 180 %conv2 = zext i1 %cmp to i32 181 ret i32 %conv2 182 } 183 184 define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind { 185 entry: 186 ; CHECK-LABEL: icmp_i8_signed 187 ; CHECK: sxtb w0, w0 188 ; CHECK-NEXT: cmp w0, w1, sxtb 189 ; CHECK-NEXT: cset w0, gt 190 %cmp = icmp sgt i8 %a, %b 191 %conv2 = zext i1 %cmp to i32 192 ret i32 %conv2 193 } 194 195 define i32 @icmp_i1_signed(i1 %a, i1 %b) nounwind { 196 entry: 197 ; CHECK-LABEL: icmp_i1_signed 198 ; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1 199 ; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1 200 ; CHECK-NEXT: cmp [[REG1]], [[REG2]] 201 ; CHECK-NEXT: cset w0, gt 202 %cmp = icmp sgt i1 %a, %b 203 %conv2 = zext i1 %cmp to i32 204 ret i32 %conv2 205 } 206 207 define i32 @icmp_i16_signed_const(i16 %a) nounwind { 208 entry: 209 ; CHECK-LABEL: icmp_i16_signed_const 210 ; CHECK: sxth w0, w0 211 ; CHECK-NEXT: cmn w0, #233 212 ; CHECK-NEXT: cset w0, lt 213 ; CHECK-NEXT: and w0, w0, #0x1 214 %cmp = icmp slt i16 %a, -233 215 %conv2 = zext i1 %cmp to i32 216 ret i32 %conv2 217 } 218 219 define i32 @icmp_i8_signed_const(i8 %a) nounwind { 220 entry: 221 ; CHECK-LABEL: icmp_i8_signed_const 222 ; CHECK: sxtb w0, w0 223 ; CHECK-NEXT: cmp w0, #124 224 ; CHECK-NEXT: cset w0, gt 225 ; CHECK-NEXT: and w0, w0, #0x1 226 %cmp = icmp sgt i8 %a, 124 227 %conv2 = zext i1 %cmp to i32 228 ret i32 %conv2 229 } 230 231 define i32 @icmp_i1_unsigned_const(i1 %a) nounwind { 232 entry: 233 ; CHECK-LABEL: icmp_i1_unsigned_const 234 ; CHECK: and w0, w0, #0x1 235 ; CHECK-NEXT: cmp w0, #0 236 ; CHECK-NEXT: cset w0, lo 237 ; CHECK-NEXT: and w0, w0, #0x1 238 %cmp = icmp ult i1 %a, 0 239 %conv2 = zext i1 %cmp to i32 240 ret i32 %conv2 241 } 242
