1 ; REQUIRES: asserts 2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s 3 ; 4 ; For Cortex-A53, shiftable operands that are not actually shifted 5 ; are not needed for an additional two cycles. 6 ; 7 ; CHECK: ********** MI Scheduling ********** 8 ; CHECK: shiftable 9 ; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0 10 ; CHECK: Successors: 11 ; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2 12 ; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2 13 ; CHECK: ********** INTERVALS ********** 14 define i64 @shiftable(i64 %A, i64 %B) { 15 %tmp0 = sub i64 %B, 20 16 %tmp1 = shl i64 %tmp0, 5; 17 %tmp2 = add i64 %A, %tmp1; 18 %tmp3 = add i64 %A, %tmp0 19 %tmp4 = mul i64 %tmp2, %tmp3 20 21 ret i64 %tmp4 22 } 23
