1 ; REQUIRES: asserts 2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s 3 4 5 @G1 = common global [100 x i32] zeroinitializer, align 4 6 @G2 = common global [100 x i32] zeroinitializer, align 4 7 8 ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling. 9 ; 10 ; CHECK-LABEL: # Machine code for function foo: Properties: <Post SSA 11 ; CHECK: SU(2): %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi 12 ; CHECK: Successors: 13 ; CHECK-NOT: ch SU(4) 14 ; CHECK: SU(3) 15 ; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}} 16 define i32 @foo() { 17 entry: 18 %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4 19 %1 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 1), align 4 20 store i32 0, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G1, i64 0, i64 0), align 4 21 %add = add nsw i32 %1, %0 22 ret i32 %add 23 } 24
