1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 2 3 define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 4 ;CHECK-LABEL: vtrni8: 5 ;CHECK: trn1.8b 6 ;CHECK: trn2.8b 7 ;CHECK-NEXT: add.8b 8 %tmp1 = load <8 x i8>, <8 x i8>* %A 9 %tmp2 = load <8 x i8>, <8 x i8>* %B 10 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> 11 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> 12 %tmp5 = add <8 x i8> %tmp3, %tmp4 13 ret <8 x i8> %tmp5 14 } 15 16 define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 17 ;CHECK-LABEL: vtrni16: 18 ;CHECK: trn1.4h 19 ;CHECK: trn2.4h 20 ;CHECK-NEXT: add.4h 21 %tmp1 = load <4 x i16>, <4 x i16>* %A 22 %tmp2 = load <4 x i16>, <4 x i16>* %B 23 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> 24 %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> 25 %tmp5 = add <4 x i16> %tmp3, %tmp4 26 ret <4 x i16> %tmp5 27 } 28 29 ; 2xi32 TRN is redundant with ZIP 30 define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 31 ;CHECK-LABEL: vtrni32: 32 ;CHECK: zip1.2s 33 ;CHECK: zip2.2s 34 ;CHECK-NEXT: add.2s 35 %tmp1 = load <2 x i32>, <2 x i32>* %A 36 %tmp2 = load <2 x i32>, <2 x i32>* %B 37 %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2> 38 %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3> 39 %tmp5 = add <2 x i32> %tmp3, %tmp4 40 ret <2 x i32> %tmp5 41 } 42 43 define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { 44 ;CHECK-LABEL: vtrnf: 45 ;CHECK: zip1.2s 46 ;CHECK: zip2.2s 47 ;CHECK-NEXT: fadd.2s 48 %tmp1 = load <2 x float>, <2 x float>* %A 49 %tmp2 = load <2 x float>, <2 x float>* %B 50 %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2> 51 %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3> 52 %tmp5 = fadd <2 x float> %tmp3, %tmp4 53 ret <2 x float> %tmp5 54 } 55 56 define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { 57 ;CHECK-LABEL: vtrnQi8: 58 ;CHECK: trn1.16b 59 ;CHECK: trn2.16b 60 ;CHECK-NEXT: add.16b 61 %tmp1 = load <16 x i8>, <16 x i8>* %A 62 %tmp2 = load <16 x i8>, <16 x i8>* %B 63 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> 64 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> 65 %tmp5 = add <16 x i8> %tmp3, %tmp4 66 ret <16 x i8> %tmp5 67 } 68 69 define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { 70 ;CHECK-LABEL: vtrnQi16: 71 ;CHECK: trn1.8h 72 ;CHECK: trn2.8h 73 ;CHECK-NEXT: add.8h 74 %tmp1 = load <8 x i16>, <8 x i16>* %A 75 %tmp2 = load <8 x i16>, <8 x i16>* %B 76 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> 77 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> 78 %tmp5 = add <8 x i16> %tmp3, %tmp4 79 ret <8 x i16> %tmp5 80 } 81 82 define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { 83 ;CHECK-LABEL: vtrnQi32: 84 ;CHECK: trn1.4s 85 ;CHECK: trn2.4s 86 ;CHECK-NEXT: add.4s 87 %tmp1 = load <4 x i32>, <4 x i32>* %A 88 %tmp2 = load <4 x i32>, <4 x i32>* %B 89 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> 90 %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> 91 %tmp5 = add <4 x i32> %tmp3, %tmp4 92 ret <4 x i32> %tmp5 93 } 94 95 define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { 96 ;CHECK-LABEL: vtrnQf: 97 ;CHECK: trn1.4s 98 ;CHECK: trn2.4s 99 ;CHECK-NEXT: fadd.4s 100 %tmp1 = load <4 x float>, <4 x float>* %A 101 %tmp2 = load <4 x float>, <4 x float>* %B 102 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> 103 %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> 104 %tmp5 = fadd <4 x float> %tmp3, %tmp4 105 ret <4 x float> %tmp5 106 } 107 108 ; Undef shuffle indices should not prevent matching to VTRN: 109 110 define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { 111 ;CHECK-LABEL: vtrni8_undef: 112 ;CHECK: trn1.8b 113 ;CHECK: trn2.8b 114 ;CHECK-NEXT: add.8b 115 %tmp1 = load <8 x i8>, <8 x i8>* %A 116 %tmp2 = load <8 x i8>, <8 x i8>* %B 117 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14> 118 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15> 119 %tmp5 = add <8 x i8> %tmp3, %tmp4 120 ret <8 x i8> %tmp5 121 } 122 123 define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { 124 ;CHECK-LABEL: vtrnQi16_undef: 125 ;CHECK: trn1.8h 126 ;CHECK: trn2.8h 127 ;CHECK-NEXT: add.8h 128 %tmp1 = load <8 x i16>, <8 x i16>* %A 129 %tmp2 = load <8 x i16>, <8 x i16>* %B 130 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14> 131 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef> 132 %tmp5 = add <8 x i16> %tmp3, %tmp4 133 ret <8 x i16> %tmp5 134 } 135
