1 ; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s 2 3 ; The following tests is to check the correctness of reversing input operand 4 ; of vext by enumerating all cases of using two undefs in shuffle masks. 5 6 define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) { 7 entry: 8 ; CHECK-LABEL: vext_6701_0: 9 ; CHECK: ext v0.8b, v1.8b, v0.8b, #4 10 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1> 11 ret <4 x i16> %x 12 } 13 14 define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) { 15 entry: 16 ; CHECK-LABEL: vext_6701_12: 17 ; CHECK: ext v0.8b, v0.8b, v0.8b, #4 18 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> 19 ret <4 x i16> %x 20 } 21 22 define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) { 23 entry: 24 ; CHECK-LABEL: vext_6701_13: 25 ; CHECK: ext v0.8b, v1.8b, v0.8b, #4 26 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1> 27 ret <4 x i16> %x 28 } 29 30 define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) { 31 entry: 32 ; CHECK-LABEL: vext_6701_14: 33 ; CHECK: ext v0.8b, v1.8b, v0.8b, #4 34 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef> 35 ret <4 x i16> %x 36 } 37 38 define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) { 39 entry: 40 ; CHECK-LABEL: vext_6701_23: 41 ; CHECK: ext v0.8b, v1.8b, v0.8b, #4 42 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1> 43 ret <4 x i16> %x 44 } 45 46 define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) { 47 entry: 48 ; CHECK-LABEL: vext_6701_24: 49 ; CHECK: ext v0.8b, v1.8b, v0.8b, #4 50 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef> 51 ret <4 x i16> %x 52 } 53 54 define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) { 55 entry: 56 ; CHECK-LABEL: vext_6701_34: 57 ; CHECK: ext v0.8b, v1.8b, v0.8b, #4 58 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef> 59 ret <4 x i16> %x 60 } 61 62 define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) { 63 entry: 64 ; CHECK-LABEL: vext_5670_0: 65 ; CHECK: ext v0.8b, v1.8b, v0.8b, #2 66 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0> 67 ret <4 x i16> %x 68 } 69 70 define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) { 71 entry: 72 ; CHECK-LABEL: vext_5670_12: 73 ; CHECK: ext v0.8b, v1.8b, v0.8b, #2 74 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0> 75 ret <4 x i16> %x 76 } 77 78 define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) { 79 entry: 80 ; CHECK-LABEL: vext_5670_13: 81 ; CHECK: ext v0.8b, v1.8b, v0.8b, #2 82 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0> 83 ret <4 x i16> %x 84 } 85 86 define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) { 87 entry: 88 ; CHECK-LABEL: vext_5670_14: 89 ; CHECK: ext v0.8b, v1.8b, v0.8b, #2 90 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef> 91 ret <4 x i16> %x 92 } 93 94 define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) { 95 entry: 96 ; CHECK-LABEL: vext_5670_23: 97 ; CHECK: ext v0.8b, v1.8b, v0.8b, #2 98 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0> 99 ret <4 x i16> %x 100 } 101 102 define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) { 103 entry: 104 ; CHECK-LABEL: vext_5670_24: 105 ; CHECK: rev32 v0.4h, v1.4h 106 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef> 107 ret <4 x i16> %x 108 } 109 110 define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) { 111 entry: 112 ; CHECK-LABEL: vext_5670_34: 113 ; CHECK: ext v0.8b, v1.8b, v0.8b, #2 114 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef> 115 ret <4 x i16> %x 116 } 117 118 define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) { 119 entry: 120 ; CHECK-LABEL: vext_7012_0: 121 ; CHECK: ext v0.8b, v1.8b, v0.8b, #6 122 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2> 123 ret <4 x i16> %x 124 } 125 126 define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) { 127 entry: 128 ; CHECK-LABEL: vext_7012_12: 129 ; CHECK: ext v0.8b, v0.8b, v0.8b, #6 130 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2> 131 ret <4 x i16> %x 132 } 133 134 define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) { 135 entry: 136 ; CHECK-LABEL: vext_7012_13: 137 ; CHECK: rev32 v0.4h, v0.4h 138 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2> 139 ret <4 x i16> %x 140 } 141 142 define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) { 143 entry: 144 ; CHECK-LABEL: vext_7012_14: 145 ; CHECK: ext v0.8b, v0.8b, v0.8b, #6 146 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef> 147 ret <4 x i16> %x 148 } 149 150 define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) { 151 entry: 152 ; CHECK-LABEL: vext_7012_23: 153 ; CHECK: ext v0.8b, v1.8b, v0.8b, #6 154 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2> 155 ret <4 x i16> %x 156 } 157 158 define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) { 159 entry: 160 ; CHECK-LABEL: vext_7012_24: 161 ; CHECK: ext v0.8b, v1.8b, v0.8b, #6 162 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef> 163 ret <4 x i16> %x 164 } 165 166 define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) { 167 entry: 168 ; CHECK-LABEL: vext_7012_34: 169 ; CHECK: ext v0.8b, v1.8b, v0.8b, #6 170 %x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef> 171 ret <4 x i16> %x 172 } 173
