1 ; RUN: llc -disable-post-ra -o - %s | FileCheck %s 2 target triple = "arm64--" 3 4 @out = internal global i32 0, align 4 5 6 ; Ensure that we transform select(C0, x, select(C1, x, y)) towards 7 ; select(C0 | C1, x, y) so we can use CMP;CCMP for the implementation. 8 ; CHECK-LABEL: test0: 9 ; CHECK: cmp w0, #7 10 ; CHECK: ccmp w1, #0, #0, ne 11 ; CHECK: csel w0, w1, w2, gt 12 ; CHECK: ret 13 define i32 @test0(i32 %v0, i32 %v1, i32 %v2) { 14 %cmp1 = icmp eq i32 %v0, 7 15 %cmp2 = icmp sgt i32 %v1, 0 16 %sel0 = select i1 %cmp1, i32 %v1, i32 %v2 17 %sel1 = select i1 %cmp2, i32 %v1, i32 %sel0 18 ret i32 %sel1 19 } 20 21 ; Usually we keep select(C0 | C1, x, y) as is on aarch64 to create CMP;CCMP 22 ; sequences. This case should be transformed to select(C0, select(C1, x, y), y) 23 ; anyway to get CSE effects. 24 ; CHECK-LABEL: test1: 25 ; CHECK-NOT: ccmp 26 ; CHECK: cmp w0, #7 27 ; CHECK: adrp x[[OUTNUM:[0-9]+]], out 28 ; CHECK: csel w[[SEL0NUM:[0-9]+]], w1, w2, eq 29 ; CHECK: cmp w[[SEL0NUM]], #13 30 ; CHECK: csel w[[SEL1NUM:[0-9]+]], w1, w2, lo 31 ; CHECK: cmp w0, #42 32 ; CHECK: csel w[[SEL2NUM:[0-9]+]], w1, w[[SEL1NUM]], eq 33 ; CHECK: str w[[SEL1NUM]], [x[[OUTNUM]], :lo12:out] 34 ; CHECK: str w[[SEL2NUM]], [x[[OUTNUM]], :lo12:out] 35 ; CHECK: ret 36 define void @test1(i32 %bitset, i32 %val0, i32 %val1) { 37 %cmp1 = icmp eq i32 %bitset, 7 38 %cond = select i1 %cmp1, i32 %val0, i32 %val1 39 %cmp5 = icmp ult i32 %cond, 13 40 %cond11 = select i1 %cmp5, i32 %val0, i32 %val1 41 %cmp3 = icmp eq i32 %bitset, 42 42 %or.cond = or i1 %cmp3, %cmp5 43 %cond17 = select i1 %or.cond, i32 %val0, i32 %val1 44 store volatile i32 %cond11, i32* @out, align 4 45 store volatile i32 %cond17, i32* @out, align 4 46 ret void 47 } 48
