1 ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s 2 3 ; 4 ; Test folding of the sign-/zero-extend into the load instruction. 5 ; 6 7 ; Unscaled 8 define i32 @load_unscaled_zext_i8_to_i32(i64 %a) { 9 ; CHECK-LABEL: load_unscaled_zext_i8_to_i32 10 ; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8] 11 ; CHECK: uxtb w0, [[REG]] 12 %1 = sub i64 %a, 8 13 %2 = inttoptr i64 %1 to i8 addrspace(256)* 14 %3 = load i8, i8 addrspace(256)* %2 15 %4 = zext i8 %3 to i32 16 ret i32 %4 17 } 18 19 define i32 @load_unscaled_zext_i16_to_i32(i64 %a) { 20 ; CHECK-LABEL: load_unscaled_zext_i16_to_i32 21 ; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8] 22 ; CHECK: uxth w0, [[REG]] 23 %1 = sub i64 %a, 8 24 %2 = inttoptr i64 %1 to i16 addrspace(256)* 25 %3 = load i16, i16 addrspace(256)* %2 26 %4 = zext i16 %3 to i32 27 ret i32 %4 28 } 29 30 define i64 @load_unscaled_zext_i8_to_i64(i64 %a) { 31 ; CHECK-LABEL: load_unscaled_zext_i8_to_i64 32 ; CHECK: ldurb w[[REG:[0-9]+]], [x0, #-8] 33 ; CHECK: ubfx x0, x[[REG]], #0, #8 34 %1 = sub i64 %a, 8 35 %2 = inttoptr i64 %1 to i8 addrspace(256)* 36 %3 = load i8, i8 addrspace(256)* %2 37 %4 = zext i8 %3 to i64 38 ret i64 %4 39 } 40 41 define i64 @load_unscaled_zext_i16_to_i64(i64 %a) { 42 ; CHECK-LABEL: load_unscaled_zext_i16_to_i64 43 ; CHECK: ldurh w[[REG:[0-9]+]], [x0, #-8] 44 ; CHECK: ubfx x0, x[[REG]], #0, #16 45 %1 = sub i64 %a, 8 46 %2 = inttoptr i64 %1 to i16 addrspace(256)* 47 %3 = load i16, i16 addrspace(256)* %2 48 %4 = zext i16 %3 to i64 49 ret i64 %4 50 } 51 52 define i64 @load_unscaled_zext_i32_to_i64(i64 %a) { 53 ; CHECK-LABEL: load_unscaled_zext_i32_to_i64 54 ; CHECK: ldur w[[REG:[0-9]+]], [x0, #-8] 55 ; CHECK: ubfx x0, x[[REG]], #0, #32 56 %1 = sub i64 %a, 8 57 %2 = inttoptr i64 %1 to i32 addrspace(256)* 58 %3 = load i32, i32 addrspace(256)* %2 59 %4 = zext i32 %3 to i64 60 ret i64 %4 61 } 62 63 define i32 @load_unscaled_sext_i8_to_i32(i64 %a) { 64 ; CHECK-LABEL: load_unscaled_sext_i8_to_i32 65 ; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8] 66 ; CHECK: sxtb w0, [[REG]] 67 %1 = sub i64 %a, 8 68 %2 = inttoptr i64 %1 to i8 addrspace(256)* 69 %3 = load i8, i8 addrspace(256)* %2 70 %4 = sext i8 %3 to i32 71 ret i32 %4 72 } 73 74 define i32 @load_unscaled_sext_i16_to_i32(i64 %a) { 75 ; CHECK-LABEL: load_unscaled_sext_i16_to_i32 76 ; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8] 77 ; CHECK: sxth w0, [[REG]] 78 %1 = sub i64 %a, 8 79 %2 = inttoptr i64 %1 to i16 addrspace(256)* 80 %3 = load i16, i16 addrspace(256)* %2 81 %4 = sext i16 %3 to i32 82 ret i32 %4 83 } 84 85 define i64 @load_unscaled_sext_i8_to_i64(i64 %a) { 86 ; CHECK-LABEL: load_unscaled_sext_i8_to_i64 87 ; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8] 88 ; CHECK: sxtb x0, [[REG]] 89 %1 = sub i64 %a, 8 90 %2 = inttoptr i64 %1 to i8 addrspace(256)* 91 %3 = load i8, i8 addrspace(256)* %2 92 %4 = sext i8 %3 to i64 93 ret i64 %4 94 } 95 96 define i64 @load_unscaled_sext_i16_to_i64(i64 %a) { 97 ; CHECK-LABEL: load_unscaled_sext_i16_to_i64 98 ; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8] 99 ; CHECK: sxth x0, [[REG]] 100 %1 = sub i64 %a, 8 101 %2 = inttoptr i64 %1 to i16 addrspace(256)* 102 %3 = load i16, i16 addrspace(256)* %2 103 %4 = sext i16 %3 to i64 104 ret i64 %4 105 } 106 107 define i64 @load_unscaled_sext_i32_to_i64(i64 %a) { 108 ; CHECK-LABEL: load_unscaled_sext_i32_to_i64 109 ; CHECK: ldur [[REG:w[0-9]+]], [x0, #-8] 110 ; CHECK: sxtw x0, [[REG]] 111 %1 = sub i64 %a, 8 112 %2 = inttoptr i64 %1 to i32 addrspace(256)* 113 %3 = load i32, i32 addrspace(256)* %2 114 %4 = sext i32 %3 to i64 115 ret i64 %4 116 } 117 118
