1 ; RUN: llc -disable-peephole -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s 2 ; RUN: llc -disable-peephole -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s 3 4 define i32 @icmp_eq_i8(i8 zeroext %a) { 5 ; CHECK-LABEL: icmp_eq_i8 6 ; CHECK: tbz {{w[0-9]+}}, #0, {{LBB.+_2}} 7 %1 = and i8 %a, 1 8 %2 = icmp eq i8 %1, 0 9 br i1 %2, label %bb1, label %bb2, !prof !0 10 bb1: 11 ret i32 1 12 bb2: 13 ret i32 0 14 } 15 16 define i32 @icmp_eq_i16(i16 zeroext %a) { 17 ; CHECK-LABEL: icmp_eq_i16 18 ; CHECK: tbz w0, #1, {{LBB.+_2}} 19 %1 = and i16 %a, 2 20 %2 = icmp eq i16 %1, 0 21 br i1 %2, label %bb1, label %bb2, !prof !0 22 bb1: 23 ret i32 1 24 bb2: 25 ret i32 0 26 } 27 28 define i32 @icmp_eq_i32(i32 %a) { 29 ; CHECK-LABEL: icmp_eq_i32 30 ; CHECK: tbz w0, #2, {{LBB.+_2}} 31 %1 = and i32 %a, 4 32 %2 = icmp eq i32 %1, 0 33 br i1 %2, label %bb1, label %bb2, !prof !0 34 bb1: 35 ret i32 1 36 bb2: 37 ret i32 0 38 } 39 40 define i32 @icmp_eq_i64_1(i64 %a) { 41 ; CHECK-LABEL: icmp_eq_i64_1 42 ; CHECK: tbz w0, #3, {{LBB.+_2}} 43 %1 = and i64 %a, 8 44 %2 = icmp eq i64 %1, 0 45 br i1 %2, label %bb1, label %bb2, !prof !0 46 bb1: 47 ret i32 1 48 bb2: 49 ret i32 0 50 } 51 52 define i32 @icmp_eq_i64_2(i64 %a) { 53 ; CHECK-LABEL: icmp_eq_i64_2 54 ; CHECK: tbz x0, #32, {{LBB.+_2}} 55 %1 = and i64 %a, 4294967296 56 %2 = icmp eq i64 %1, 0 57 br i1 %2, label %bb1, label %bb2, !prof !0 58 bb1: 59 ret i32 1 60 bb2: 61 ret i32 0 62 } 63 64 define i32 @icmp_ne_i8(i8 zeroext %a) { 65 ; CHECK-LABEL: icmp_ne_i8 66 ; CHECK: tbnz w0, #0, {{LBB.+_2}} 67 %1 = and i8 %a, 1 68 %2 = icmp ne i8 %1, 0 69 br i1 %2, label %bb1, label %bb2, !prof !0 70 bb1: 71 ret i32 1 72 bb2: 73 ret i32 0 74 } 75 76 define i32 @icmp_ne_i16(i16 zeroext %a) { 77 ; CHECK-LABEL: icmp_ne_i16 78 ; CHECK: tbnz w0, #1, {{LBB.+_2}} 79 %1 = and i16 %a, 2 80 %2 = icmp ne i16 %1, 0 81 br i1 %2, label %bb1, label %bb2, !prof !0 82 bb1: 83 ret i32 1 84 bb2: 85 ret i32 0 86 } 87 88 define i32 @icmp_ne_i32(i32 %a) { 89 ; CHECK-LABEL: icmp_ne_i32 90 ; CHECK: tbnz w0, #2, {{LBB.+_2}} 91 %1 = and i32 %a, 4 92 %2 = icmp ne i32 %1, 0 93 br i1 %2, label %bb1, label %bb2, !prof !0 94 bb1: 95 ret i32 1 96 bb2: 97 ret i32 0 98 } 99 100 define i32 @icmp_ne_i64_1(i64 %a) { 101 ; CHECK-LABEL: icmp_ne_i64_1 102 ; CHECK: tbnz w0, #3, {{LBB.+_2}} 103 %1 = and i64 %a, 8 104 %2 = icmp ne i64 %1, 0 105 br i1 %2, label %bb1, label %bb2, !prof !0 106 bb1: 107 ret i32 1 108 bb2: 109 ret i32 0 110 } 111 112 define i32 @icmp_ne_i64_2(i64 %a) { 113 ; CHECK-LABEL: icmp_ne_i64_2 114 ; CHECK: tbnz x0, #32, {{LBB.+_2}} 115 %1 = and i64 %a, 4294967296 116 %2 = icmp ne i64 %1, 0 117 br i1 %2, label %bb1, label %bb2, !prof !0 118 bb1: 119 ret i32 1 120 bb2: 121 ret i32 0 122 } 123 124 define i32 @icmp_slt_i8(i8 zeroext %a) { 125 ; FAST-LABEL: icmp_slt_i8 126 ; FAST: tbnz w0, #7, {{LBB.+_2}} 127 %1 = icmp slt i8 %a, 0 128 br i1 %1, label %bb1, label %bb2, !prof !0 129 bb1: 130 ret i32 1 131 bb2: 132 ret i32 0 133 } 134 135 define i32 @icmp_slt_i16(i16 zeroext %a) { 136 ; FAST-LABEL: icmp_slt_i16 137 ; FAST: tbnz w0, #15, {{LBB.+_2}} 138 %1 = icmp slt i16 %a, 0 139 br i1 %1, label %bb1, label %bb2, !prof !0 140 bb1: 141 ret i32 1 142 bb2: 143 ret i32 0 144 } 145 146 define i32 @icmp_slt_i32(i32 %a) { 147 ; CHECK-LABEL: icmp_slt_i32 148 ; CHECK: tbnz w0, #31, {{LBB.+_2}} 149 %1 = icmp slt i32 %a, 0 150 br i1 %1, label %bb1, label %bb2, !prof !0 151 bb1: 152 ret i32 1 153 bb2: 154 ret i32 0 155 } 156 157 define i32 @icmp_slt_i64(i64 %a) { 158 ; CHECK-LABEL: icmp_slt_i64 159 ; CHECK: tbnz x0, #63, {{LBB.+_2}} 160 %1 = icmp slt i64 %a, 0 161 br i1 %1, label %bb1, label %bb2, !prof !0 162 bb1: 163 ret i32 1 164 bb2: 165 ret i32 0 166 } 167 168 define i32 @icmp_sge_i8(i8 zeroext %a) { 169 ; FAST-LABEL: icmp_sge_i8 170 ; FAST: tbz w0, #7, {{LBB.+_2}} 171 %1 = icmp sge i8 %a, 0 172 br i1 %1, label %bb1, label %bb2, !prof !0 173 bb1: 174 ret i32 1 175 bb2: 176 ret i32 0 177 } 178 179 define i32 @icmp_sge_i16(i16 zeroext %a) { 180 ; FAST-LABEL: icmp_sge_i16 181 ; FAST: tbz w0, #15, {{LBB.+_2}} 182 %1 = icmp sge i16 %a, 0 183 br i1 %1, label %bb1, label %bb2, !prof !0 184 bb1: 185 ret i32 1 186 bb2: 187 ret i32 0 188 } 189 190 define i32 @icmp_sle_i8(i8 zeroext %a) { 191 ; FAST-LABEL: icmp_sle_i8 192 ; FAST: tbnz w0, #7, {{LBB.+_2}} 193 %1 = icmp sle i8 %a, -1 194 br i1 %1, label %bb1, label %bb2, !prof !0 195 bb1: 196 ret i32 1 197 bb2: 198 ret i32 0 199 } 200 201 define i32 @icmp_sle_i16(i16 zeroext %a) { 202 ; FAST-LABEL: icmp_sle_i16 203 ; FAST: tbnz w0, #15, {{LBB.+_2}} 204 %1 = icmp sle i16 %a, -1 205 br i1 %1, label %bb1, label %bb2, !prof !0 206 bb1: 207 ret i32 1 208 bb2: 209 ret i32 0 210 } 211 212 define i32 @icmp_sle_i32(i32 %a) { 213 ; CHECK-LABEL: icmp_sle_i32 214 ; CHECK: tbnz w0, #31, {{LBB.+_2}} 215 %1 = icmp sle i32 %a, -1 216 br i1 %1, label %bb1, label %bb2, !prof !0 217 bb1: 218 ret i32 1 219 bb2: 220 ret i32 0 221 } 222 223 define i32 @icmp_sle_i64(i64 %a) { 224 ; CHECK-LABEL: icmp_sle_i64 225 ; CHECK: tbnz x0, #63, {{LBB.+_2}} 226 %1 = icmp sle i64 %a, -1 227 br i1 %1, label %bb1, label %bb2, !prof !0 228 bb1: 229 ret i32 1 230 bb2: 231 ret i32 0 232 } 233 234 define i32 @icmp_sgt_i8(i8 zeroext %a) { 235 ; FAST-LABEL: icmp_sgt_i8 236 ; FAST: tbz w0, #7, {{LBB.+_2}} 237 %1 = icmp sgt i8 %a, -1 238 br i1 %1, label %bb1, label %bb2, !prof !0 239 bb1: 240 ret i32 1 241 bb2: 242 ret i32 0 243 } 244 245 define i32 @icmp_sgt_i16(i16 zeroext %a) { 246 ; FAST-LABEL: icmp_sgt_i16 247 ; FAST: tbz w0, #15, {{LBB.+_2}} 248 %1 = icmp sgt i16 %a, -1 249 br i1 %1, label %bb1, label %bb2, !prof !0 250 bb1: 251 ret i32 1 252 bb2: 253 ret i32 0 254 } 255 256 define i32 @icmp_sgt_i32(i32 %a) { 257 ; CHECK-LABEL: icmp_sgt_i32 258 ; CHECK: tbz w0, #31, {{LBB.+_2}} 259 %1 = icmp sgt i32 %a, -1 260 br i1 %1, label %bb1, label %bb2, !prof !0 261 bb1: 262 ret i32 1 263 bb2: 264 ret i32 0 265 } 266 267 define i32 @icmp_sgt_i64(i64 %a) { 268 ; FAST-LABEL: icmp_sgt_i64 269 ; FAST: tbz x0, #63, {{LBB.+_2}} 270 %1 = icmp sgt i64 %a, -1 271 br i1 %1, label %bb1, label %bb2, !prof !0 272 bb1: 273 ret i32 1 274 bb2: 275 ret i32 0 276 } 277 278 ; Test that we don't fold the 'and' instruction into the compare. 279 define i32 @icmp_eq_and_i32(i32 %a, i1 %c) { 280 ; CHECK-LABEL: icmp_eq_and_i32 281 ; CHECK: and [[REG:w[0-9]+]], w0, #0x4 282 ; CHECK-NEXT: cbz [[REG]], {{LBB.+_3}} 283 %1 = and i32 %a, 4 284 br i1 %c, label %bb0, label %bb2 285 bb0: 286 %2 = icmp eq i32 %1, 0 287 br i1 %2, label %bb1, label %bb2, !prof !0 288 bb1: 289 ret i32 1 290 bb2: 291 ret i32 0 292 } 293 294 !0 = !{!"branch_weights", i32 0, i32 2147483647} 295 !1 = !{!"branch_weights", i32 2147483647, i32 0} 296
